Publication Details

DFT Flow for RT Level Digital Circuits Using iFCoRT System

RŮŽIČKA Richard. DFT Flow for RT Level Digital Circuits Using iFCoRT System. In: Proceedings of the Seventh International Scientific Conference Electronic Computers and Informatics ECI 2006. Košice, 2006, pp. 292-297. ISBN 80-8073-598-0.
Czech title
Návrhový tok návrhu pro snadnou testovatelnost číslicových systémů na úrovni RT s využitím systému iFCoRT
Type
conference paper
Language
english
Authors
Keywords

Testability Analysis, Testability Verification, Design-for-Testability

Abstract

Our team performs some research activities at the field of testability in past years. These activities results in testability analysis, testability verification, test scheduling and test controller synthesis methodologies. All methodologies are described formally using language of mathematics and theoretical computer science and are based on a formal model of the RT level digital circuit. These tasks can be performed by the iFCoRT system (I path Based, Formally Described and Proved Concept of RTL Digital Circuits Testability). This paper describes how the system can be used during design-for-testability process - a design flow of a testable RT level digital circuit.

Published
2006
Pages
292-297
Proceedings
Proceedings of the Seventh International Scientific Conference Electronic Computers and Informatics ECI 2006
Conference
7TH International Scientific Conference Electronic Computers and Informatics 2006, Herľany, SK
ISBN
80-8073-598-0
Place
Košice, SK
BibTeX
@INPROCEEDINGS{FITPUB8178,
   author = "Richard R\r{u}\v{z}i\v{c}ka",
   title = "DFT Flow for RT Level Digital Circuits Using iFCoRT System",
   pages = "292--297",
   booktitle = "Proceedings of the Seventh International Scientific Conference Electronic Computers and Informatics ECI 2006",
   year = 2006,
   location = "Ko\v{s}ice, SK",
   ISBN = "80-8073-598-0",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8178"
}
Back to top