Conference paper

SMRČKA Aleš, ŘEHÁK Vojtěch, VOJNAR Tomáš, ŠAFRÁNEK David, MATOUŠEK Petr and ŘEHÁK Zdeněk. Verifying VHDL Design with Multiple Clocks in SMV. In: Proceedings of FMICS 2006. Bonn, 2006, pp. 140-155.
Publication language:english
Original title:Verifying VHDL Design with Multiple Clocks in SMV
Title (cs):Verifying VHDL Design with Multiple Clocks in SMV
Proceedings:Proceedings of FMICS 2006
Conference:Formal Methods for Industrial Critical Systems
Place:Bonn, DE
model checking, hardware, VHDL, multiple clocks, SMV
The paper considers the problem of model checking real-life VHDL-based hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, ie. designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.
   author = {Ale{\v{s}} Smr{\v{c}}ka and Vojt{\v{e}}ch
	{\v{R}}eh{\'{a}}k and Tom{\'{a}}{\v{s}} Vojnar and
	David {\v{S}}afr{\'{a}}nek and Petr Matou{\v{s}}ek
	and Zden{\v{e}}k {\v{R}}eh{\'{a}}k},
   title = {Verifying VHDL Design with Multiple Clocks in SMV},
   pages = {140--155},
   booktitle = {Proceedings of FMICS 2006},
   year = 2006,
   location = {Bonn, DE},
   language = {english},
   url = {}

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