Conference paper

STRAKA Martin. VHDL Design of Educational, Modern and Open-Architecture CPU. In: Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4. Brno: Brno University of Technology, 2007, pp. 457-461. ISBN 978-80-214-3410-3.
Publication language:english
Original title:VHDL Design of Educational, Modern and Open-Architecture CPU
Title (cs):Návrh pokročilé architektury procesoru ve VHDL
Pages:457-461
Proceedings:Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4
Conference:Student EEICT 2007
Place:Brno, CZ
Year:2007
ISBN:978-80-214-3410-3
Publisher:Brno University of Technology
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Keywords
VHDL, pipeline, CPU, cache, prediction unit
Annotation

The paper deals with design of a modern, open-architecture CPU utilizable for educational

purposes. It is expected that use of the CPU in the educational process will greatly contribute

to deeper understanding of key-topics taught in the area of modern architectures. Our

CPU is based on the Von-Neumann architecture, equipped with a five-stage pipeline, cache

memory unit and simple branch prediction unit. The architecture is designed in VHDL including

set of 16 instructions. Rich variety of educative tasks can be performed by means

of the CPU. It has been both successfully simulated in ModelSim and synthesized in Precision

RTL Synthesis in order to be implemented in FPGA and utilized in practice as a real

working CPU.

BibTeX:
@INPROCEEDINGS{
   author = {Martin Straka},
   title = {VHDL Design of Educational, Modern and Open-Architecture CPU},
   pages = {457--461},
   booktitle = {Proceedings of the 13th Conference STUDENT EEICT 2007 Volume
	4},
   year = {2007},
   location = {Brno, CZ},
   publisher = {Brno University of Technology},
   ISBN = {978-80-214-3410-3},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8339}
}

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