Conference paper

STRAKA Martin, TOBOLA Jiří and KOTÁSEK Zdeněk. Checker Design for On-line Testing of Xilinx FPGA Communication. In: The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Rome: IEEE Computer Society, 2007, pp. 152-160. ISBN 0-7695-2885-6.
Publication language:english
Original title:Checker Design for On-line Testing of Xilinx FPGA Communication
Title (cs):Checker Design for On-line Testing of Xilinx FPGA Communication
Pages:152-160
Proceedings:The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Conference:The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Place:Rome, IT
Year:2007
ISBN:0-7695-2885-6
Publisher:IEEE Computer Society
Files: 
+Type Name Title Size Last modified
icondft07.pdf171 KB2008-04-01 10:54:48
^ Select all
With selected:
Keywords
Communication Protocol Testing, Fault Tolerant Systems,
checker design
Annotation

In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.

BibTeX:
@INPROCEEDINGS{
   author = {Martin Straka and Ji{\v{r}}{\'{i}} Tobola and Zden{\v{e}}k
	Kot{\'{a}}sek},
   title = {Checker Design for On-line Testing of Xilinx FPGA
	Communication},
   pages = {152--160},
   booktitle = {The 22nd IEEE International Symposium on Defect and Fault
	Tolerance in VLSI Systems},
   year = {2007},
   location = {Rome, IT},
   publisher = {IEEE Computer Society},
   ISBN = {0-7695-2885-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8353}
}

Your IPv4 address: 54.161.53.213
Switch to IPv6 connection

DNSSEC [dnssec]