Journal article

SEKANINA Lukáš. Evolutionary Functional Recovery in Virtual Reconfigurable Circuits. ACM Journal on Emerging Technologies in Computing Systems. 2007, vol. 3, no. 2, pp. 1-22. ISSN 1550-4832.
Publication language:english
Original title:Evolutionary Functional Recovery in Virtual Reconfigurable Circuits
Title (cs):Evolutionary Functional Recovery in Virtual Reconfigurable Circuits
Pages:1-22
Year:2007
Journal:ACM Journal on Emerging Technologies in Computing Systems, Vol. 3, No. 2, US
ISSN:1550-4832
URL:http://www.fit.vutbr.cz/~sekanina/publ/ject/ject07.pdf [PDF]
Keywords
hardware, logic design, reliability, reconfigurable circuit, evolutionary algorithm
Annotation
A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial run-time reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices. 
BibTeX:
@ARTICLE{
   author = {Luk{\'{a}}{\v{s}} Sekanina},
   title = {Evolutionary Functional Recovery in Virtual Reconfigurable
	Circuits},
   pages = {1--22},
   journal = {ACM Journal on Emerging Technologies in Computing Systems},
   volume = {3},
   number = {2},
   year = {2007},
   ISSN = {1550-4832},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8376}
}

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