Conference paper

RŮŽIČKA Richard and STRNADEL Josef. Test Controller Synthesis Constrained by Circuit Testability Analysis. In: Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society Press, 2007, pp. 626-633. ISBN 0-7695-2978-X.
Publication language:english
Original title:Test Controller Synthesis Constrained by Circuit Testability Analysis
Title (cs):Syntéza řadiče testu založená na analýze testovatelnosti obvodu
Pages:626-633
Proceedings:Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Conference:10th EUROMICRO Conference on Digital System Design
Place:Los Alamitos, US
Year:2007
ISBN:0-7695-2978-X
Publisher:IEEE Computer Society Press
Keywords
testability analysis, test controller, RTL digital circuit diagnostics
Annotation
In the paper, a method for test controller synthesis based on testability analysis results is presented. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of elements in the circuit during the test application process. Proposed testability analysis method is efficient for RT level pipelined data-path circuit. Close coupling of testability analysis and test controller synthesis saves the test cost in terms of area overhead, test time and fault coverage. All processes are described formally.
BibTeX:
@INPROCEEDINGS{
   author = {Richard R{\r{u}}{\v{z}}i{\v{c}}ka and Josef Strnadel},
   title = {Test Controller Synthesis Constrained by Circuit Testability
	Analysis},
   pages = {626--633},
   booktitle = {Proceedings of 10th Euromicro Conference on Digital System
	Design, Architectures, Methods and Tools},
   year = {2007},
   location = {Los Alamitos, US},
   publisher = {IEEE Computer Society Press},
   ISBN = {0-7695-2978-X},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8443}
}

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