Conference paper

MIKUŠEK Petr. Návrh a implementace jednotky pro analýzu paketů. In: Proceedings of the 11th Conference and Competition STUDENT EEICT 2005. Brno: Brno University of Technology, 2005, pp. 145-148. ISBN 80-214-2888-0.
Publication language:czech
Original title:Návrh a implementace jednotky pro analýzu paketů
Title (en):Design and Implementation of Processing Unit for Packet Analysis
Pages:145-148
Proceedings:Proceedings of the 11th Conference and Competition STUDENT EEICT 2005
Conference:STUDENT EEICT 2005
Place:Brno, CZ
Year:2005
ISBN:80-214-2888-0
Publisher:Brno University of Technology
Keywords
RISC, FPGA, VHDL, COMBO6, packet analysis
Annotation

This paper presents architecture of Header Field Extractor processor, which is dedicated for packet analysis. It extracts specific control information from packet's headers, which are important for further packet processing. Processor is based on RISC architecture and it is controlled by instruction set dedicated for packet analysis. As a target technology the Field Programmable Gate Array (FPGA) is supposed.

BibTeX:
@INPROCEEDINGS{
   author = {Petr Miku{\v{s}}ek},
   title = {N{\'{a}}vrh a implementace jednotky pro anal{\'{y}}zu
	paket{\r{u}}},
   pages = {145--148},
   booktitle = {Proceedings of the 11th Conference and Competition STUDENT
	EEICT 2005},
   year = {2005},
   location = {Brno, CZ},
   publisher = {Brno University of Technology},
   ISBN = {80-214-2888-0},
   language = {czech},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8448}
}

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