Conference paper

ŠKARVADA Jaroslav. RT Level Test Optimization for Low Power Consumption. In: MEMICS proceedings 2007. Brno: Ing. Zdeněk Novotný, CSc., 2007, pp. 185-192. ISBN 978-80-7355-077-6.
Publication language:english
Original title:RT Level Test Optimization for Low Power Consumption
Title (cs):Optimalizace testu na úrovni RT pro nízký příkon
Pages:185-192
Proceedings:MEMICS proceedings 2007
Conference:MEMICS'07 -- 3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Place:Brno, CZ
Year:2007
ISBN:978-80-7355-077-6
Publisher:Ing. Zdeněk Novotný, CSc.
Keywords
Register transfer level, power consumption optimization, test vectors reordering, scan cells reordering
Annotation
The paper deals with low power consumption test optimization for register transfer level (RTL) circuits. A model of circuit under test (CUT), based on the theory of sets and relations is defined. In the model, the power consumption is seen as a parameter depending on circuit structure and input data used for the test. Optimization method to reduce power consumption during test application, is presented.
BibTeX:
@INPROCEEDINGS{
   author = {Jaroslav {\v{S}}karvada},
   title = {RT Level Test Optimization for Low Power Consumption},
   pages = {185--192},
   booktitle = {MEMICS proceedings 2007},
   year = {2007},
   location = {Brno, CZ},
   publisher = {Ing. Zden{\v{e}}k Novotn{\'{y}}, CSc.},
   ISBN = {978-80-7355-077-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8504}
}

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