Conference paper

STRAKA Martin, KOTÁSEK Zdeněk and WINTER Jan. Digital Systems Architectures Based on On-line Checkers. In: 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008, pp. 81-87. ISBN 978-0-7695-3277-6.
Publication language:english
Original title:Digital Systems Architectures Based on On-line Checkers
Title (cs):Digital Systems Architectures Based on On-line Checkers
Pages:81-87
Proceedings:11th EUROMICRO Conference on Digital System Design DSD 2008
Conference:11th EUROMICRO Conference on Digital Systems Design 2008
Place:Parma, IT
Year:2008
ISBN:978-0-7695-3277-6
Publisher:IEEE Computer Society
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Keywords
Fault Tolerant Systems, simple circuit, checker, FPGA, on-line testing, protocols
Annotation
In this paper, we present a methodology for generating
VHDL descriptions of hardware checkers is presented. It is
shown how the methodology can be used to generate on-line
checkers of communication protocols, counters, decoders,
registers, comparators, etc. It is also demonstrated how a
checker for more complex structures can be developed. We
describe the possibilities of utilizing this approach in the design
of Fault Tolerant Systems (FTS). Experimental results
in terms of FPGA resources needed to synthesize different
types of checkers are presented.
BibTeX:
@INPROCEEDINGS{
   author = {Martin Straka and Zden{\v{e}}k Kot{\'{a}}sek and Jan Winter},
   title = {Digital Systems Architectures Based on On-line Checkers},
   pages = {81--87},
   booktitle = {11th EUROMICRO Conference on Digital System Design DSD 2008},
   year = {2008},
   location = {Parma, IT},
   publisher = {IEEE Computer Society},
   ISBN = {978-0-7695-3277-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8621}
}

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