Conference paper

GAJDA Zbyšek and SEKANINA Lukáš. Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming. In: Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009, pp. 1599-1604. ISBN 978-1-4244-2958-5.
Publication language:english
Original title:Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming
Title (cs):Optimalizace polymorfních obvodů na úrovni hradel pomocí kartézského genetického programování
Pages:1599-1604
Proceedings:Proc. of 2009 IEEE Congress on Evolutionary Computation
Conference:IEEE Congress on Evolutionary Computation
Place:NA, US
Year:2009
ISBN:978-1-4244-2958-5
Publisher:IEEE Computational Intelligence Society
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Keywords
polymorphic circuit, circuit synthesis, evolutionary design, cartesian genetic programming
Annotation
Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits of variable input size.
BibTeX:
@INPROCEEDINGS{
   author = {Zby{\v{s}}ek Gajda and Luk{\'{a}}{\v{s}} Sekanina},
   title = {Gate-Level Optimization of Polymorphic Circuits Using
	Cartesian Genetic Programming},
   pages = {1599--1604},
   booktitle = {Proc. of 2009 IEEE Congress on Evolutionary Computation},
   year = {2009},
   location = {NA, US},
   publisher = {IEEE Computational Intelligence Society},
   ISBN = {978-1-4244-2958-5},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8949}
}

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