Journal article

DVOŘÁK Václav and MIKUŠEK Petr. Firmware Optimization for Embedded Logic Control. IFAC-PapersOnLine. Laxenburg: IFAC, 2009, vol. 2009, no. 1, pp. 109-114. ISBN 978-3-902661-69-2. ISSN 1474-6670.
Publication language:czech
Original title:Firmware Optimization for Embedded Logic Control
Title (en):Firmware Optimzation for Embedded Logic Control
Pages:109-114
Book:4th IFAC Workshop Discrete-Event System Design
Place:AT
Year:2009
ISBN:978-3-902661-69-2
Journal:IFAC-PapersOnLine, Vol. 2009, No. 1, Laxenburg, AT
ISSN:1474-6670
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Keywords
Incompletely specified functions, multi-terminal BDDs, iterative disjunctive decomposition, firmware design, multi-way branching
Annotation
This paper presents a new method to represent a subclass of multiple-output incompletely specified functions by means of multi-terminal binary decision diagrams (MTBDDs). Algorithm to reduce the cost and width of MTBDDs is presented. A software CAD tool makes use of iterative decomposition to obtain a MTBDD data structure that can be directly mapped to firmware in a form of chained dispatch tables. On a practical example it is shown that there is a space-time trade-off between the amount of memory required for all dispatch tables in a control store and the speed of firmware execution. Support for multi-way branching in a micro-sequencer is assumed.
BibTeX:
@ARTICLE{
   author = {V{\'{a}}clav Dvo{\v{r}}{\'{a}}k and Petr Miku{\v{s}}ek},
   title = {Firmware Optimization for Embedded Logic Control},
   pages = {109--114},
   booktitle = {4th IFAC Workshop Discrete-Event System Design},
   journal = {IFAC-PapersOnLine},
   volume = {2009},
   number = {1},
   year = {2009},
   ISBN = {978-3-902661-69-2},
   ISSN = {1474-6670},
   language = {czech},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9074}
}

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