Conference paper

ZACHARIÁŠOVÁ Marcela. Hardware Accelerated Functional Verification. In: Proceedings of the 17th Conference STUDENT EEICT 2011. Brno: Faculty of Information Technology BUT, 2011, pp. 321-323. ISBN 978-80-214-4272-6.
Publication language:english
Original title:Hardware Accelerated Functional Verification
Title (cs):Hardwarově akcelerovaná funkční verifikace
Pages:321-323
Proceedings:Proceedings of the 17th Conference STUDENT EEICT 2011
Conference:Student EEICT 2011
Place:Brno, CZ
Year:2011
ISBN:978-80-214-4272-6
Publisher:Faculty of Information Technology BUT
URL:http://www.feec.vutbr.cz/EEICT/2011/sbornik/02-Magisterske%20projekty/10-Pocitacove%20systemy/10-xsimko03.pdf [PDF]
Keywords
functional verification, testbench, SystemVerilog, hardware acceleration, FPGA
Annotation
Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. We introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.
BibTeX:
@INPROCEEDINGS{
   author = {Marcela Zachari{\'{a}}{\v{s}}ov{\'{a}}},
   title = {Hardware Accelerated Functional Verification},
   pages = {321--323},
   booktitle = {Proceedings of the 17th Conference STUDENT EEICT 2011},
   year = {2011},
   location = {Brno, CZ},
   publisher = {Faculty of Information Technology BUT},
   ISBN = {978-80-214-4272-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9705}
}

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