Smart Multicore Embedded SYstems

Czech title:Smart Multicore Embedded SYstems
Reseach leader:Zemčík Pavel
Team leaders:Hruška Tomáš, Smrž Pavel
Agency:Artemis Joint Undertaking - Seventh Research Framework Programme
Code:100230 - SMECY
Start:2010-02-01
End:2013-01-31
Keywords:multi-core architectures, embedded systems
Annotation:
SMECY envisions that recently emerged multi-core technologies will rapidly develop to massively parallel computing environments, which due to improved performance, energy and cost properties will, in a few years, extensively penetrate the embedded system industry sectors. This will affect and shape the whole business landscape, e.g. semiconductor vendors need to be capable of offering advanced multi-core platforms to diverse application sectors, Intellectual Property (IP) providers need to re-target existing and develop new solutions to be compatible with evolving multi-core platforms and the need of embedded system houses, in addition to product architecture adaptations and renewing their system, architecture, software and hardware development processes. The complexity of future smart multi-core embedded systems requires holistic system integration because of stringent constraints on e.g. performance and time to market that can only be mastered using a design approach that optimizes interaction between SoC design and Embedded Software approaches. Therefore, many companies that traditionally have a culture rooted in nano and microelectronics express an urgent need in acquiring know-how and competences in embedded software. Equally urgent is the need of embedded system houses to be able to transform their current product assets to use multi-cores and at the same time to establish development processes in order to fully exploit them. The mission of the SMECY project is to develop new programming technologies enabling the exploitation of many (100s) core architectures. Multi-core technologies are strategic to keep and win market shares in all areas of embedded systems. ARTEMIS covers well most aspects of embedded systems, but efficient programming of multi-core architectures for various resources-constrained embedded system applications, such as consumer, wireless and some transportation fields, is still a grand challenge waiting to be solved. The goal of this ARTEMIS project is to launch an ambitious European initiative to allow Europe to catch up with Asia (e.g. teams funded by JST/CREST programmes) and USA (e.g. PARLAB in Berkeley, Parallel@illinois and Pervasive Parallelism Laboratory in Stanford) and to enable Europe to become the leader. The key outcomes of the SMECY project are programming and design methods, multi-core programmable architectural solutions and associated supporting tools that enable a holistic integration of multi-core SoC design and embedded software to master smart system design of future smart multi-core embedded systems in different applications, e.g. consumer, wireless, communication and transportation.

Products

2014Robust Automatic Vector Accelerator Compiler, software, 2014
Authors: Hruška Tomáš, Husár Adam, Masařík Karel
2012A Cross-platform Discrete Wavelet Transform Library version 2, software, 2012
Authors: Bařina David, Zemčík Pavel
 Set of image processing algorithms resulting from SMECY, software, 2012
Authors: Bařina David, Juránek Roman, Dubská Markéta, Nečas Ondřej, Zemčík Pavel
2010A Cross-platform Discrete Wavelet Transform Library, software, 2010
Authors: Bařina David, Zemčík Pavel
 Hierarchy of Parts, software, 2010
Authors: Nečas Ondřej, Herout Adam, Zemčík Pavel, Bařina David
 Multiplatform Framework for Object Detection, software, 2010
Authors: Juránek Roman, Zemčík Pavel, Hradiš Michal, Herout Adam
 Multiplatform Software for Line Detection, software, 2010
Authors: Dubská Markéta, Herout Adam, Zemčík Pavel

Publications

2014HAVEL Jiří, DUBSKÁ Markéta, HEROUT Adam and JOŠTH Radovan. Real-Time Detection of Lines using Parallel Coordinates and CUDA. Journal of Real-Time Image Processing. 2014, vol. 2014, no. 9, pp. 205-216. ISSN 1861-8200.
2013DUBSKÁ Markéta, HEROUT Adam and HAVEL Jiří. Real-Time Precise Detection of Regular Grids and Matrix Codes. Journal of Real-Time Image Processing. 2013, vol. 2013, no. 1, p. 15. ISSN 1861-8200.
 HAVEL Jiří, HEROUT Adam and DUBSKÁ Markéta. Vanishing Points in Point-to-Line Mappings and Other Line Parameterizations. Pattern Recognition Letters. 2013, vol. 2013, no. 34, pp. 703-708. ISSN 0167-8655.
2012DOLÍHAL Luděk, HRUŠKA Tomáš and MASAŘÍK Karel. Testing of an automatically generated compiler, Review of retargetable testing system. International Journal on Advances in Software. 2012, vol. 2012, no. 1, pp. 15-26. ISSN 1942-2628.
 DOLÍHAL Luděk, HRUŠKA Tomáš and MASAŘÍK Karel. Usage of simulators in testing system. In: Industrial Simulation Conference. Brno: EUROSIS, 2012, pp. 74-78. ISBN 978-90-77381-71-7.
 JURÁNEK Roman, HRADIŠ Michal and ZEMČÍK Pavel. Real-time Algorithms of Object Detection with Classifiers. Real-Time System. Rijeka: InTech - Open Access Publisher, 2012, pp. 1-22. ISBN 9789535105107.
2011BAŘINA David and NEČAS Ondřej. Using Hierarchy of Parts for Image Classification. In: Proceedings of the 17th Conference STUDENT EEICT 2011. Brno: Brno University of Technology, 2011, pp. 532-536. ISBN 978-80-214-4273-3.
 BAŘINA David. Gabor Wavelets in Image Processing. In: Proceedings of the 17th Conference STUDENT EEICT 2011. Brno: Brno University of Technology, 2011, pp. 522-526. ISBN 978-80-214-4273-3.
 DOLÍHAL Luděk and HRUŠKA Tomáš. Porting of C library, Testing of generated compiler. In: InfoWare 2011. Luxembourg: International Academy, Research, and Industry Association, 2011, pp. 125-130. ISBN 978-1-61208-008-6.
 DUBSKÁ Markéta, HAVEL Jiří and HEROUT Adam. Real-Time Detection of Lines using Parallel Coordinates and OpenGL. In: Proceedings of SCCG 2011. Bratislava: Comenius University in Bratislava, 2011, p. 7. ISBN 978-80-223-3018-3.
 DUBSKÁ Markéta, HEROUT Adam and HAVEL Jiří. PClines - Line Detection Using Parallel Coordinates. In: Proceedings of CVPR 2011. Colorado Springs: IEEE Computer Society, 2011, pp. 1489-1494. ISBN 978-1-4577-0393-5.
 ĎURFINA Lukáš, KŘOUSTEK Jakub, ZEMEK Petr, KOLÁŘ Dušan, HRUŠKA Tomáš, MASAŘÍK Karel and MEDUNA Alexander. Design of a Retargetable Decompiler for a Static Platform-Independent Malware Analysis. In: The 5th International Conference on Information Security and Assurance. Brno: Springer Verlag, 2011, pp. 72-86. ISBN 978-3-642-23140-7.
 ĎURFINA Lukáš, KŘOUSTEK Jakub, ZEMEK Petr, KOLÁŘ Dušan, HRUŠKA Tomáš, MASAŘÍK Karel and MEDUNA Alexander. Design of a Retargetable Decompiler for a Static Platform-Independent Malware Analysis. International Journal of Security and Its Applications. Daejeon: Science & Engineering Research Support Center, 2011, vol. 5, no. 4, pp. 91-106. ISSN 1738-9976.
 KŘOUSTEK Jakub, PŘIKRYL Zdeněk, KOLÁŘ Dušan and HRUŠKA Tomáš. Retargetable Multi-level Debugging in HW/SW Codesign. In: The 23rd International Conference on Microelectronics (ICM 2011). Hammamet: Institute of Electrical and Electronics Engineers, 2011, pp. 1-6. ISBN 978-1-4577-2209-7.
 KŘOUSTEK Jakub, ŽIDEK Stanislav, KOLÁŘ Dušan and MEDUNA Alexander. Scattered Context Grammars with Priority. International Journal of Advanced Research in Computer Science. Udaipur: International Journal of Advanced Research in Computer Science, 2011, vol. 2, no. 4, pp. 1-6. ISSN 0976-5697.
 PŘIKRYL Zdeněk. Advanced Methods of Microprocessor Simulation. Information Sciences and Technologies Bulletin of the ACM Slovakia. Bratislava: Vydavateľstvo STU, 2011, vol. 3, no. 3, pp. 1-13. ISSN 1338-1237.
 PŘIKRYL Zdeněk, KŘOUSTEK Jakub, HRUŠKA Tomáš and KOLÁŘ Dušan. Fast Just-In-Time Translated Simulator for ASIP Design. In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011, pp. 279-282. ISBN 978-1-4244-9753-9.
 PŘIKRYL Zdeněk, KŘOUSTEK Jakub, HRUŠKA Tomáš and KOLÁŘ Dušan. Fast Translated Simulation of ASIPs. OpenAccess Series in Informatics (OASIcs). Wadern: Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik, 2011, vol. 16, no. 1, pp. 93-100. ISSN 2190-6807.
 PŘIKRYL Zdeněk, KŘOUSTEK Jakub, HRUŠKA Tomáš, KOLÁŘ Dušan, MASAŘÍK Karel and HUSÁR Adam. Design and Simulation of High Performance Parallel Architectures Using the ISAC Language. GSTF International Journal on Computing. Singapur: Global Science & Technology Forum, 2011, vol. 1, no. 2, pp. 97-106. ISSN 2010-2283.
2010HRADIŠ Michal, BERAN Vítězslav, ŘEZNÍČEK Ivo, HEROUT Adam, BAŘINA David, VLČEK Adam and ZEMČÍK Pavel. Brno University of Technology at TRECVid 2010. In: TRECVID 2010: Participant Notebook Papers and Slides. Gaithersburg, MD: National Institute of Standards and Technology, 2010, p. 11.
 HUSÁR Adam, TRMAČ Miloslav, HRANÁČ Jan, HRUŠKA Tomáš, MASAŘÍK Karel, KOLÁŘ Dušan and PŘIKRYL Zdeněk. Automatic C Compiler Generation from Architecture Description Language ISAC. In: 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010, pp. 84-91. ISBN 978-80-87342-10-7.
 PŘIKRYL Zdeněk, HRUŠKA Tomáš, MASAŘÍK Karel and HUSÁR Adam. Fast Cycle-Accurate Compiled Simulator. In: 10th IFAC Workshop on Programmable Devices and Embedded Systems, PDeS 2010. Pszczyna: IFAC, 2010, pp. 97-102. ISBN 978-3-902661-95-1. ISSN 1474-6670.
 PŘIKRYL Zdeněk, KŘOUSTEK Jakub, HRUŠKA Tomáš and KOLÁŘ Dušan. Fast Translated Simulation of ASIPs. In: 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010, pp. 135-142. ISBN 978-80-87342-10-7.
 PŘIKRYL Zdeněk, MASAŘÍK Karel, HRUŠKA Tomáš and HUSÁR Adam. Generated Cycle-Accurate Profiler for C Language. In: 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010, pp. 263-268. ISBN 978-0-7695-4171-6.
 TRMAČ Miloslav, HUSÁR Adam, HRANÁČ Jan, HRUŠKA Tomáš and MASAŘÍK Karel. Instructor Selector Generation from Architecture Description. In: 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010, pp. 167-174. ISBN 978-80-87342-10-7.