Projects

 

Design and hardware implementation of a patent-invention machine
Reseach leader:Sekanina Lukáš
Team leaders:Bidlo Michal, Čapka Ladislav, Dvořák Václav, Gajda Zbyšek, Jaroš Jiří, Kobliha Miloš, Martínek Tomáš, Mikušek Petr, Schwarz Josef, Slaný Karel, Šimek Václav, Vašíček Zdeněk, Žaloudek Luděk
Agency:GAČR
Code:GA102/07/0850
Start:2007
End:2009
Keywords:evolutionary design, field programmable gate array, patent
Annotation:
This basic research project deals with a new approach to the design and implementation of intelligent machines. The aim of this project is to design and implement a machine that will be able to automatically generate human-competitive and patentable inventions. This machine will be based on a genetic programming system accelerated using a field programmable gate array that integrates reconfigurable logic as well as PowerPC processors on a single chip. The machine will be utilized to produce human-competitive and patentable inventions in areas of digital circuit design, scheduling, image processing, predicting, molecular design etc. As this machine will be available as a relatively small embedded device it can be utilized to generate intelligent solutions to the dynamically emerging problems in real-world applications, e.g. in mobile systems, adaptive traffic controllers, robots etc. This is a multidisciplinary project of artificial intelligence and various scientific and engineering fields.

Products

Publications

2012Sekanina, L.: Evolvable hardware, Handbook of Natural Computing, Berlin, DE, Springer, 2012, p. 1657-1705, ISBN 978-3-540-92909-3
 Vašíček, Z.: Acceleration Methods for Evolutionary Design of Digital Circuits, Brno, CZ, 2012, p. 162
2010Jaroš, J.: Evolutionary Design of Collective Communications on Wormhole Networks, Brno, CZ, UPSY FIT VUT, 2010, p. 149
 Jaroš, J.: Evolutionary Design of Collective Communications on Wormhole Networks, Brno, CZ, VUTIUM, 2010, p. 183, ISBN 978-80-214-4208-5
 Vašíček, Z., Sekanina, L.: Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units, In: Computing and Informatics, Vol. 29, No. 6, 2010, Bratislava, SK, p. 1359-1371, ISSN 1335-9150
2009Bidlo, M., Vašíček, Z.: Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits, In: Proceedings 2009 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2009, p. 423-430, ISBN 978-0-7695-3714-6
 Bidlo, M., Vašíček, Z.: Development of Combinational Circuits Using Non-Uniform Cellular Automata: Initial Results, In: Genetic and Evolutionary Computation, New York, US, ACM, 2009, p. 1839-1840, ISBN 978-1-60558-325-9
 Bidlo, M., Vašíček, Z.: Investigating Gate-Level Evolutionary Development of Combinational Multipliers Using Enhanced Cellular Automata-Based Model, In: Proc. of 2009 IEEE Congress on Evolutionary Computation, NA, US, IEEE CIS, 2009, p. 2241-2248, ISBN 978-1-4244-2958-5
 Bidlo, M.: Evolutionary Design of Generic Structures Using Instruction-Based Development, Brno, CZ, UPSY FIT VUT, 2009, p. 124
 Dvořák, V., Mikušek, P.: Firmware Optimization for Embedded Logic Control, In: IFAC-PapersOnLine, Vol. 2009, No. 1, Laxenburg, AT, p. 109-114, ISBN 978-3-902661-69-2, ISSN 1474-6670
 Gajda, Z.: Návrh a optimalizace polymorfních obvodů, In: Počítačová architektura a Diagnostika 2009, Zlín, CZ, UTB ve Zlíně, 2009, p. 63-67, ISBN 978-80-7318-847-4
 Jaroš, J., Schwarz, J.: Parallel BMDA with an Aggregation of Probability Models, In: Proceeding of 2009 IEEE Congress on Evolutionary Computation, Trondheim, NO, IEEE CIS, 2009, p. 1683-1690, ISBN 978-1-4244-2959-2
 Jaroš, J.: Evolutionary Optimization of Multistage Interconnection Networks Performance, In: Proceeding of Genetic and Evolutionary Computation Conference, GECCO 2009, New York, US, ACM, 2009, p. 1537-1544, ISBN 978-1-60558-325-9
 Mikušek, P., Dvořák, V.: Heuristic Synthesis of MTBDDs Based On Local Width Minimization, In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Znojmo, CZ, MUNI, 2009, p. 235-235, ISBN 978-80-87342-04-6
 Mikušek, P., Dvořák, V.: Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization, In: 12th EUROMICRO Conference on Digital System Design DSD 2009, Patras, GR, IEEE CS, 2009, p. 605-608, ISBN 978-0-7695-3782-5
 Mikušek, P.: Dekompoziční techniky pro aplikačně specifické systémy, In: Počítačové architektury a diagnostika 2009, Zlín, CZ, UTB ve Zlíně, 2009, p. 118-123, ISBN 978-80-7318-847-4
 Mikušek, P.: Multi-Terminal BDD Synthesis and Applications, In: Proceedings 19th International Conference on Field Programmable Logic and Applications (FPL), Prague, CZ, IEEE CS, 2009, p. 721-722, ISBN 978-1-4244-3892-1
 Sekanina, L., Růžička, R., Gajda, Z.: Polymorphic FIR Filters with Backup Mode Enabling Power Savings, In: Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2009, p. 43-50, ISBN 978-0-7695-3714-6
 Sekanina, L., Vašíček, Z., Růžička, R., Bidlo, M., Jaroš, J., Švenda, P.: Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům, Praha, CZ, Academia, 2009, p. 328, ISBN 978-80-200-1729-1
 Sekanina, L.: Evolvable Hardware: From Applications to Implications for the Theory of Computation, In: Proc. of the 8th Int. Conference on Unconventional Computation, Berlin, DE, Springer, 2009, p. 24-36, ISBN 978-3-642-03744-3
 Slaný, K.: Comparison of CGP and Age-Layered CGP Performance in Image Operator Evolution, In: Genetic Programming, 12th European Conference, EuroGP 2009, Tübingen, DE, Springer, 2009, p. 351-361, ISBN 978-3-642-01180-1, ISSN 0302-9743
 Slaný, K.: Towards the Automatic Evolutionary Prediction of the FOREX Market Behaviour, In: Proceedings of the 2009 International Conference on Adaptive and Intelligent Systems, Klagenfurt, AT, IEEE CS, 2009, p. 141-145, ISBN 978-0-7695-3827-3
 Vašíček, Z., Bidlo, M., Sekanina, L., Torresen, J., Glette, K., Furuholmen, M.: Evolution of Impulse Bursts Noise Filters, In: Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2009, p. 27-34, ISBN 978-0-7695-3714-6
 Vašíček, Z., Sekanina, L.: Efficient Hardware Accelerator for Symbolic Regression Problems, In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Znojmo, CZ, MUNI, 2009, p. 192-199, ISBN 978-80-87342-04-6
 Žaloudek, L., Sekanina, L., Šimek, V.: GPU Accelerators for Evolvable Cellular Automata, In: Computation World: Future Computing, Service Computation, Adaptive, Content, Cognitive, Patterns, Athens, GR, IEEE, 2009, p. 533-537, ISBN 978-0-7695-3862-4
 Žaloudek, L.: Akcelerace evoluce pravidel celulárních automatů na GPU, In: Počítačové architektury a diagnostika 2009, Zlín, CZ, UTB ve Zlíně, 2009, p. 173-178, ISBN 978-80-7318-847-4
2008Bidlo, M., Škarvada, J.: Instruction-based development: From evolution to generic structures of digital circuits, In: International Journal of Knowledge-Based and Intelligent Engineering Systems, Vol. 12, No. 3, 2008, Amsterdam, NL, p. 221-236, ISSN 1327-2314
 Bidlo, M., Vašíček, Z.: Gate-Level Evolutionary Development Using Cellular Automata, In: 2008 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, ICSP, 2008, p. 11-18, ISBN 978-0-7695-3166-3
 Dvořák, V., Mikušek, P.: LUT Cascade-Based Implementations of Allocators, In: Proc. of the 25th Convention of EEE in Israel, New York, US, IEEE CS, 2008, p. 85-89, ISBN 978-1-4244-2482-5
 Dvořák, V.: Communication Performance of Mesh- and Ring-Based NoCs, In: Proceedings of the 7th Int. Conference on Networking, New York, US, IEEE CS, 2008, p. 156-161, ISBN 978-0-7695-3106-9
 Dvořák, V.: Embedded Firmware Development with Multi-Way Branching, In: Proc. of the 3rd Int. Coference on Systems, New York, US, IEEE CS, 2008, p. 317-322, ISBN 978-0-7695-3105-2
 Dvořák, V.: Implementation of Combinational and Sequential Functions in Embedded Firmware, In: International Journal of Software Engineering and Its Applications, Vol. 2, No. 1, 2008, Daegu, KR, p. 43-54, ISSN 1738-9984
 Hornby, G., S., Sekanina, L., Haddow, P., C. (editors): Proceedings of Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2008, p. 444, ISBN 978-3-540-85856-0
 Jaroš, J., Dvořák, V.: An Evolutionary Design Technique for Collective Communications on Optimal Diameter-Degree Networks, In: 2008 Genetic and Evolutionary Computational Conference GECCO, New York, US, ACM, 2008, p. 1539-1546, ISBN 978-1-60558-131-6
 Jaroš, J., Schwarz, J.: Evolutionary Design of Wormhole Switched Collective Communications, In: Proceedings of Junior Scientist Conference 2008, Vienna, AT, TUV, 2008, p. 2, ISBN 978-3-200-01612-5
 Jaroš, J.: Evolutionary Design of Fault Tolerant Collective Communications, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2008, p. 261-272, ISBN 978-3-540-85856-0
 Kobliha, M.: Evolutionary Optimization of Dynamic Problems: a Short Survey, In: 14th International Conference on Soft Computing, Brno, CZ, FS ČVUT, 2008, p. 26-31, ISBN 978-80-214-3675-6
 Mikušek, P., Dvořák, V.: On Lookup Table Cascade-Based Realizations of Arbiters, In: 11th EUROMICRO Conference on Digital System Design DSD 2008, Parma, IT, IEEE CS, 2008, p. 795-802, ISBN 978-0-7695-3277-6
 Mikušek, P., Dvořák, V.: On Lookup Table Cascade-Based Realizations of Arbiters, In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Znojmo, CZ, MUNI, 2008, p. 261-261, ISBN 978-80-7355-082-0
 Pečenka, T., Sekanina, L., Kotásek, Z.: Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability, In: ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 3, 2008, US, p. 1-21, ISSN 1084-4309
 Schwarz, J., Jaroš, J.: Parallel Bivariate Marginal Distribution Algorithm with Probability Model Migration, Linkage in Evolutionary Computation, Berlin / Heidelberg, DE, Springer, 2008, p. 3-23, ISBN 978-3-540-85067-0
 Slaný, K.: Branch Predictor On-line Evolutionary System, In: 2008 Genetic and Evolutionary Computation Conference GECCO, New York, US, ACM, 2008, p. 1643-1648, ISBN 978-1-60558-131-6
 Vašíček, Z., Sekanina, L.: Hardware Accelerators for Cartesian Genetic Programming, In: Eleventh European Conference on Genetic Programming, Berlin, DE, Springer, 2008, p. 230-241, ISBN 978-3-540-78670-2
 Vašíček, Z., Sekanina, L.: Novel Hardware Implementation of Adaptive Median Filters, In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Bratislava, SK, IEEE CS, 2008, p. 110-115, ISBN 978-1-4244-2276-0
 Vašíček, Z., Žádník, M., Sekanina, L., Tobola, J.: On Evolutionary Synthesis of Linear Transforms, In: Evolvable Systems: From Biology > to > Hardware, Berlin, DE, Springer, 2008, p. 141-152, ISBN 978-3-540-85856-0
 Žaloudek, L.: Sebereplikace ve výpočetních systémech, In: Počítačové architektury a diagnostika 2008, Liberec, CZ, TUL, 2008, p. 131-136, ISBN 978-80-7372-378-1
2007Bidlo, M.: Evolutionary Design of Generic Combinational Multipliers Using Development, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2007, p. 77-88, ISBN 978-3-540-74625-6
 Čapka, L., Vašíček, Z.: Investigating the Influence of Mutation Operators in Cartesian Genetic Programming, In: 13th International Conference on Soft Computing, Brno, CZ, FSI VUT, 2007, p. 43-47, ISBN 978-80-214-3473-8
 Dvořák, V., Jaroš, J., Ohlídal, M.: Optimum Topology-Aware Scheduling of Collective Communications, In: Proceedings of The Sixth International Conference on Networking, New York, US, IEEE CS, 2007, p. 6, ISBN 0-7695-2805-8
 Dvořák, V.: Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware, In: Journal of Software, Vol. 2, No. 5, 2007, Oulu, FI, p. 52-63, ISSN 1796-217X
 Dvořák, V.: Implementation of Combinational and Sequential Functions in Embedded Firmware, In: Proceedings of the 2007 International Conference on Intelligent Pervasive Computing (IPC-07), Los Alamitos, California, US, IEEE CS, 2007, p. 80-85, ISBN 978-0-7695-3006-2
 Dvořák, V.: LUT Cascade-Based Architectures for High Productivity Embedded Systems, In: International Review on Computers and Software , Vol. 2, No. 4, 2007, Naples, Italy, IT, p. 357-365, ISSN 1828-600X
 Dvořák, V.: Space-Time Trade-offs in SW Evaluation of Boolean Functions, In: Proceedings of The Second International Conference on Systems, New York, US, IEEE CS, 2007, p. 6, ISBN 0-7695-2807-4
 Dvořák, V.: Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software, In: Proceedings of 14th Annual IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, Los Alamitos, US, IEEE CS, 2007, p. 178-185, ISBN 0-7695-2772-8
 Jaroš, J., Ohlídal, M., Dvořák, V.: An Evolutionary Approach to Collective Communication Scheduling, In: 2007 Genetic and Evolutionary Computation Conference, New York, US, ACM, 2007, p. 2037-2044, ISBN 978-1-59593-697-4
 Jaroš, J., Schwarz, J.: Parallel BMDA with Probability Model Migration, In: Proceeding of 2007 IEEE Congress on Evolutionary Computation, Singapore, SG, IEEE CS, 2007, p. 1059-1066, ISBN 1-4244-1340-0
 Jaroš, J.: Optimalizace kolektivních komunikací na wormhole propojovacích sítích, In: Sborník příspěvků semináře Počítačové architektury a diagnostika pro studenty doktorského studia, Plzeň, CZ, ZČU v Plzni, 2007, p. 6, ISBN 987-80-7043-605-9
 Kobliha, M., Schwarz, J.: Self-Organizing Migrating Algorithm for Dynamic Problems: An Experimental study, In: 13th International Conference on Soft Computing, Brno, CZ, FSI VUT, 2007, p. 24-29, ISBN 978-80-214-3473-8
 Sekanina, L., Martínek, T.: Evolving Image Operators Directly in Hardware, Genetic and Evolutionary Computation for Image Processing and Analysis, New York, US, Hindawi, 2007, p. 93-112, ISBN 978-977-454-001-1
 Sekanina, L.: Evolved Computing Devices and the Implementation Problem, In: Minds and Machines, Vol. 17, No. 3, 2007, NL, p. 311-329, ISSN 0924-6495
 Sekanina, L.: Vztah mezi abstraktním a fyzickým výpočtem v kontextu evolučního návrhu, In: Kognice a umělý život VII, Opava, CZ, SLU, 2007, p. 305-310, ISBN 9788072484126
 Schwarz, J., Jaroš, J., Očenášek, J.: Migration of Probabilistic Models for Island-Based Bivariate EDA Algorithm, In: 2007 Genetic and Evolutionary Computational Conference, New York, US, ACM, 2007, p. 631-631, ISBN 9781595936974
 Slaný, K., Dvořák, V.: Evolutionary Designed Branch Predictors, In: 13th International Conference on Soft Computing, Brno, CZ, FSI VUT, 2007, p. 18-23, ISBN 978-80-214-3473-8
 Slaný, K., Sekanina, L.: Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP, In: Genetic Programming, 10th European Conference, EuroGP 2007, Berlin, DE, Springer, 2007, p. 311-320, ISBN 978-3-540-71602-0
 Vašíček, Z., Sekanina, L.: An Area-Efficient Alternative to Adaptive Median Filtering in FPGAs, In: Proc. of 2007 International Conference on Field Programmable Logic and Applications, Los Alamitos, US, IEEE CS, 2007, p. 216-221, ISBN 1424410606
 Vašíček, Z., Sekanina, L.: An Evolvable Hardware System in Xilinx Virtex II Pro FPGA, In: International Journal of Innovative Computing and Applications , Vol. 1, No. 1, 2007, Geneva, CH, p. 63-73, ISSN 1751-648X
 Vašíček, Z., Sekanina, L.: Evaluation of a New Platform For Image Filter Evolution, In: Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2007, p. 577-584, ISBN 076952866X
 Vašíček, Z., Sekanina, L.: Reducing the Area on a Chip Using a Bank of Evolved Filters, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2007, p. 222-232, ISBN 978-3-540-74625-6