Projects

 

Smart Multicore Embedded SYstems
Reseach leader:Zemčík Pavel
Team leaders:Hruška Tomáš, Smrž Pavel
Agency:Artemis JU
Code:SMECY
Start:2010
End:2013
Keywords:multi-core architectures, embedded systems
Annotation:
SMECY envisions that recently emerged multi-core technologies will rapidly develop to massively parallel computing environments, which due to improved performance, energy and cost properties will, in a few years, extensively penetrate the embedded system industry sectors. This will affect and shape the whole business landscape, e.g. semiconductor vendors need to be capable of offering advanced multi-core platforms to diverse application sectors, Intellectual Property (IP) providers need to re-target existing and develop new solutions to be compatible with evolving multi-core platforms and the need of embedded system houses, in addition to product architecture adaptations and renewing their system, architecture, software and hardware development processes. The complexity of future smart multi-core embedded systems requires holistic system integration because of stringent constraints on e.g. performance and time to market that can only be mastered using a design approach that optimizes interaction between SoC design and Embedded Software approaches. Therefore, many companies that traditionally have a culture rooted in nano and microelectronics express an urgent need in acquiring know-how and competences in embedded software. Equally urgent is the need of embedded system houses to be able to transform their current product assets to use multi-cores and at the same time to establish development processes in order to fully exploit them. The mission of the SMECY project is to develop new programming technologies enabling the exploitation of many (100s) core architectures. Multi-core technologies are strategic to keep and win market shares in all areas of embedded systems. ARTEMIS covers well most aspects of embedded systems, but efficient programming of multi-core architectures for various resources-constrained embedded system applications, such as consumer, wireless and some transportation fields, is still a grand challenge waiting to be solved. The goal of this ARTEMIS project is to launch an ambitious European initiative to allow Europe to catch up with Asia (e.g. teams funded by JST/CREST programmes) and USA (e.g. PARLAB in Berkeley, Parallel@illinois and Pervasive Parallelism Laboratory in Stanford) and to enable Europe to become the leader. The key outcomes of the SMECY project are programming and design methods, multi-core programmable architectural solutions and associated supporting tools that enable a holistic integration of multi-core SoC design and embedded software to master smart system design of future smart multi-core embedded systems in different applications, e.g. consumer, wireless, communication and transportation.

Products

2012A Cross-platform Discrete Wavelet Transform Library version 2, software, 2012
Authors: Bařina David, Zemčík Pavel
 Robust Automatic Vector Accelerator Compiler, software, 2012
Authors: Hruška Tomáš, Husár Adam, Masařík Karel
 Set of image processing algorithms resulting from SMECY, software, 2012
Authors: Bařina David, Juránek Roman, Dubská Markéta, Nečas Ondřej, Zemčík Pavel

Publications

2013Dubská, M., Herout, A., Havel, J.: Real-Time Precise Detection of Regular Grids and Matrix Codes, In: Journal of Real-Time Image Processing , Vol. 2013, No. 1, DE, p. 15, ISSN 1861-8200
 Havel, J., Herout, A., Dubská, M.: Vanishing Points in Point-to-Line Mappings and Other Line Parameterizations, In: Pattern Recognition Letters, Vol. 2013, No. 34, NL, p. 703-708, ISSN 0167-8655
2012Dolíhal, L., Hruška, T., Masařík, K.: Testing of an automatically generated compiler, Review of retargetable testing system, In: International Journal on Advances in Software, Vol. 2012, No. 1, US, p. 15-26, ISSN 1942-2628
 Dolíhal, L., Hruška, T., Masařík, K.: Usage of simulators in testing system, In: Industrial Simulation Conference, Brno, CZ, EUROSIS, 2012, p. 74-78, ISBN 978-90-77381-71-7
 Dubská, M., Havel, J., Herout, A., Jošth, R.: Real-Time Detection of Lines using Parallel Coordinates and CUDA, In: Journal of Real-Time Image Processing , Vol. 2012, No. 12, DE, p. 1-12, ISSN 1861-8200
 Juránek, R., Hradiš, M., Zemčík, P.: Real-time Algorithms of Object Detection with Classifiers, Real-Time System, Rijeka, HR, InTech, 2012, p. 1-22, ISBN 9789535105107
 Juránek, R.: Acceleration of Object Detection Using Classifiers, Brno, CZ, FIT VUT, 2012, p. 1-77
2011Bařina, D., Nečas, O.: Using Hierarchy of Parts for Image Classification, In: Proceedings of the 17th Conference STUDENT EEICT 2011, Brno, CZ, VUT v Brně, 2011, p. 532-536, ISBN 978-80-214-4273-3
 Bařina, D.: Gabor Wavelets in Image Processing, In: Proceedings of the 17th Conference STUDENT EEICT 2011, Brno, CZ, VUT v Brně, 2011, p. 522-526, ISBN 978-80-214-4273-3
 Dolíhal, L., Hruška, T.: Porting of C library, Testing of generated compiler, In: InfoWare 2011, Luxembourg, LU, IARIA, 2011, p. 125-130, ISBN 978-1-61208-008-6
 Dubská, M., Havel, J., Herout, A.: Real-Time Detection of Lines using Parallel Coordinates and OpenGL, In: Proceedings of SCCG 2011, Bratislava, SK, UNIBA, 2011, p. 7, ISBN 978-80-223-3018-3
 Dubská, M., Herout, A., Havel, J.: PClines - Line Detection Using Parallel Coordinates, In: Proceedings of CVPR 2011, Colorado Springs, US, IEEE CS, 2011, p. 1489-1494, ISBN 978-1-4577-0393-5
 Ďurfina, L., Křoustek, J., Zemek, P., Kolář, D., Hruška, T., Masařík, K., Meduna, A.: Design of a Retargetable Decompiler for a Static Platform-Independent Malware Analysis, In: The 5th International Conference on Information Security and Assurance, Brno, CZ, Springer, 2011, p. 72-86, ISBN 978-3-642-23140-7
 Ďurfina, L., Křoustek, J., Zemek, P., Kolář, D., Hruška, T., Masařík, K., Meduna, A.: Design of a Retargetable Decompiler for a Static Platform-Independent Malware Analysis, In: International Journal of Security and Its Applications, Vol. 5, No. 4, 2011, Daejeon, KR, p. 91-106, ISSN 1738-9976
 Křoustek, J., Přikryl, Z., Kolář, D., Hruška, T.: Retargetable Multi-level Debugging in HW/SW Codesign, In: The 23rd International Conference on Microelectronics (ICM 2011), Hammamet, TN, IEEE, 2011, p. 1-6, ISBN 978-1-4577-2209-7
 Křoustek, J., Židek, S., Kolář, D., Meduna, A.: Scattered Context Grammars with Priority, In: International Journal of Advanced Research in Computer Science, Vol. 2, No. 4, 2011, Udaipur, IN, p. 1-6, ISSN 0976-5697
 Přikryl, Z., Křoustek, J., Hruška, T., Kolář, D., Masařík, K., Husár, A.: Design and Simulation of High Performance Parallel Architectures Using the ISAC Language, In: GSTF International Journal on Computing, Vol. 1, No. 2, 2011, Singapur, SG, p. 97-106, ISSN 2010-2283
 Přikryl, Z., Křoustek, J., Hruška, T., Kolář, D.: Fast Just-In-Time Translated Simulator for ASIP Design, In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cottbus, DE, IEEE CS, 2011, p. 279-282, ISBN 978-1-4244-9753-9
 Přikryl, Z., Křoustek, J., Hruška, T., Kolář, D.: Fast Translated Simulation of ASIPs, In: OpenAccess Series in Informatics (OASIcs), Vol. 16, No. 1, 2011, Wadern, DE, p. 93-100, ISSN 2190-6807
 Přikryl, Z.: Advanced Methods of Microprocessor Simulation, In: Information Sciences and Technologies Bulletin of the ACM Slovakia, Vol. 3, No. 3, 2011, Bratislava, SK, p. 1-13, ISSN 1338-1237
2010Hradiš, M., Beran, V., Řezníček, I., Herout, A., Bařina, D., Vlček, A., Zemčík, P.: Brno University of Technology at TRECVid 2010, In: TRECVID 2010: Participant Notebook Papers and Slides, Gaithersburg, MD, US, NIST, 2010, p. 11
 Husár, A., Trmač, M., Hranáč, J., Hruška, T., Masařík, K., Kolář, D., Přikryl, Z.: Automatic C Compiler Generation from Architecture Description Language ISAC, In: 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2010, p. 84-91, ISBN 978-80-87342-10-7
 Přikryl, Z., Hruška, T., Masařík, K., Husár, A.: Fast Cycle-Accurate Compiled Simulator, In: 10th IFAC Workshop on Programmable Devices and Embedded Systems, PDeS 2010, Pszczyna, PL, IFAC, 2010, p. 97-102, ISBN 978-3-902661-95-1, ISSN 1474-6670
 Přikryl, Z., Křoustek, J., Hruška, T., Kolář, D.: Fast Translated Simulation of ASIPs, In: 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2010, p. 135-142, ISBN 978-80-87342-10-7
 Přikryl, Z., Masařík, K., Hruška, T., Husár, A.: Generated Cycle-Accurate Profiler for C Language, In: 13th EUROMICRO Conference on Digital System Design, DSD'2010, Lille, FR, IEEE CS, 2010, p. 263-268, ISBN 978-0-7695-4171-6
 Trmač, M., Husár, A., Hranáč, J., Hruška, T., Masařík, K.: Instructor Selector Generation from Architecture Description, In: 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2010, p. 167-174, ISBN 978-80-87342-10-7