Článek ve sborníku konference

SEKANINA Lukáš. Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. In: 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007, s. 243-246. ISBN 1424411610.
Jazyk publikace:angličtina
Název publikace:Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
Název (cs):Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
Strany:243-246
Sborník:2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Konference:The 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Místo vydání:Gliwice, PL
Rok:2007
ISBN:1424411610
Vydavatel:IEEE Computer Society
URL:http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf [PDF]
Klíčová slova
digital circuit, polymorphic gate, adder, testing
Anotace
TBD
BibTeX:
@INPROCEEDINGS{
   author = {Lukáš Sekanina},
   title = {Design and Analysis of a New Self-Testing Adder Which
	Utilizes Polymorphic Gates},
   pages = {243--246},
   booktitle = {2007 IEEE Workshop on Design and Diagnostics of Electronic
	Circuits and Systems},
   year = {2007},
   location = {Gliwice, PL},
   publisher = {IEEE Computer Society},
   ISBN = {1424411610},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.cs?id=8310}
}

Vaše IPv4 adresa: 184.73.40.21
Přepnout na IPv6 spojení

DNSSEC [dnssec]