Článek ve sborníku konference

 
Straka, M., Kotásek, Z., Winter, J.: Digital Systems Architectures Based on On-line Checkers, In: 11th EUROMICRO Conference on Digital System Design DSD 2008, Parma, IT, IEEE CS, 2008, s. 81-87, ISBN 978-0-7695-3277-6
Jazyk publikace:angličtina
Název publikace:Digital Systems Architectures Based on On-line Checkers
Název (cs):Digital Systems Architectures Based on On-line Checkers
Strany:81-87
Sborník:11th EUROMICRO Conference on Digital System Design DSD 2008
Konference:11th EUROMICRO Conference on Digital Systems Design 2008
Místo vydání:Parma, IT
Rok:2008
ISBN:978-0-7695-3277-6
Vydavatel:IEEE Computer Society
Soubory: 
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icondsd08.pdf130 KB2008-10-08 11:45:50
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Klíčová slova
Fault Tolerant Systems, simple circuit, checker, FPGA, on-line testing, protocols
Anotace
In this paper, we present a methodology for generating
VHDL descriptions of hardware checkers is presented. It is
shown how the methodology can be used to generate on-line
checkers of communication protocols, counters, decoders,
registers, comparators, etc. It is also demonstrated how a
checker for more complex structures can be developed. We
describe the possibilities of utilizing this approach in the design
of Fault Tolerant Systems (FTS). Experimental results
in terms of FPGA resources needed to synthesize different
types of checkers are presented.
BibTeX:
@INPROCEEDINGS{
   author = {Martin Straka and Zdeněk Kotásek and Jan Winter},
   title = {Digital Systems Architectures Based on On-line Checkers},
   pages = {81--87},
   booktitle = {11th EUROMICRO Conference on Digital System Design DSD 2008},
   year = {2008},
   location = {Parma, IT},
   publisher = {IEEE Computer Society},
   ISBN = {978-0-7695-3277-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8621}
}