Článek ve sborníku konference | |
| Straka, M., Mičulka, L., Kaštil, J., Kotásek, Z.: Test Platform for Fault Tolerant Systems Design Qualities Verification, In: 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Tallin, EE, IEEE CS, 2012, s. 336-341, ISBN 978-1-4673-1185-4 | | Jazyk publikace: | angličtina |
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| Název publikace: | Test Platform for Fault Tolerant Systems Design Qualities Verification |
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| Název (cs): | Testovací platforma pro ověřování kvality navrhu systémů odolných proti poruchám |
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| Strany: | 336-341 |
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| Sborník: | 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems |
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| Konference: | IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2012 |
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| Místo vydání: | Tallin, EE |
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| Rok: | 2012 |
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| ISBN: | 978-1-4673-1185-4 |
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| Vydavatel: | IEEE Computer Society |
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| Klíčová slova |
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| controller, fault tolernat system, FPGA, SEU, injector, test platform |
| Anotace |
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Příspěvek popisuje metodologii pro testovaní kvality návrhu systémů odolných proti poruchám, která je založena na externím SEU injektoru. Architektura testovací platformy je prezentována a principy její funkčnosti jsou popsány. |
| Abstrakt |
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In this paper, a methodology for fault tolerant systems design qualities verification is presented together with recovery technique for fault tolerant system after soft errors occurrence in SRAM-based FPGA. First, the principles of test platform based on external SEU injector are presented, all components of test platform and their role during SEU simulation are described. Then, the recovery technique based on the generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The controller is used for the identification of faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in FPGA structure as well. The first experiments with test platform and reconfiguration controller are discussed in this paper. |
| BibTeX: |
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@INPROCEEDINGS{
author = {Martin Straka and Lukáš Mičulka and Jan Kaštil and Zdeněk
Kotásek},
title = {Test Platform for Fault Tolerant Systems Design Qualities
Verification},
pages = {336--341},
booktitle = {15th IEEE International Symposium on Design and Diagnostics
of Electronic Circuits and Systems},
year = {2012},
location = {Tallin, EE},
publisher = {IEEE Computer Society},
ISBN = {978-1-4673-1185-4},
language = {english},
url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9903}
} |
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