Conference paperRŮŽIČKA Richard, SEKANINA Lukáš and PROKOP Roman. Physical Demonstration of Polymorphic Self-checking Circuits. In: Proc. of the 14th IEEE Int. On-Line Testing Symposium. Los Alamitos: IEEE Computer Society, 2008, pp. 31-36. ISBN 978-0-7695-3264-6. | Publication language: | english |
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Original title: | Physical Demonstration of Polymorphic Self-checking Circuits |
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Title (cs): | Physical Demonstration of Polymorphic Self-checking Circuits |
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Pages: | 31-36 |
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Proceedings: | Proc. of the 14th IEEE Int. On-Line Testing Symposium |
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Conference: | 14th IEEE International On-line Testing Symposium 2008 |
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Place: | Los Alamitos, US |
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Year: | 2008 |
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ISBN: | 978-0-7695-3264-6 |
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Publisher: | IEEE Computer Society |
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URL: | [PDF] |
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Files: | |
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| Keywords |
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digital circuit, polymorphic gate, self-checking, adder |
Annotation |
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Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized in a self-checking polymorphic adder. This paper presents an experimental evaluation of this novel implementation. |
BibTeX: |
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@INPROCEEDINGS{
author = {Richard R{\r{u}}{\v{z}}i{\v{c}}ka and
Luk{\'{a}}{\v{s}} Sekanina and Roman Prokop},
title = {Physical Demonstration of Polymorphic
Self-checking Circuits},
pages = {31--36},
booktitle = {Proc. of the 14th IEEE Int. On-Line Testing Symposium},
year = {2008},
location = {Los Alamitos, US},
publisher = {IEEE Computer Society},
ISBN = {978-0-7695-3264-6},
language = {english},
url = {http://www.fit.vutbr.cz/research/view_pub.php.en?id=8652}
} |
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