Conference paper

 
Herrman, T.: Identifikace testovatelných bloků v obvodu na úrovni RT, In: Počítačové architektury a diagnostika 2008, Liberec, CZ, TUL, 2008, p. 25-35, ISBN 978-80-7372-378-1
Publication language:czech
Original title:Identifikace testovatelných bloků v obvodu na úrovni RT
Title (en):Testable Block Identification in RT Level Circuits
Pages:25-35
Proceedings:Počítačové architektury a diagnostika 2008
Conference:Počítačové architektury a diagnostika 2008
Place:Liberec, CZ
Year:2008
ISBN:978-80-7372-378-1
Publisher:Liberec University of Technology
Keywords
Testable Block, formal model, testability, scan method, evolutionary algorithm, RT level
Annotation
The formal model of Testable block on RT level is presented in the paper. Principles of identification of Testable block are defined. In the next part the details of implementation of methodology is described. At the end of paper is stated contend of doctoral thesis.
BibTeX:
@INPROCEEDINGS{
   author = {Tomáš Herrman},
   title = {Identifikace testovatelných bloků v obvodu na úrovni RT},
   pages = {25--35},
   booktitle = {Počítačové architektury a diagnostika 2008},
   year = {2008},
   location = {Liberec, CZ},
   publisher = {Liberec University of Technology},
   ISBN = {978-80-7372-378-1},
   language = {czech},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8812}
}