Journal article

 
Kotásek, Z., Straka, M.: The Design of On-line Checkers and Their Use in Verification and Testing, In: Acta Electrotechnica et Informatica, Vol. 2009, No. 3, SK, p. 8-15, ISSN 1335-8243
Publication language:english
Original title:The Design of On-line Checkers and Their Use in Verification and Testing
Title (cs):The Design of On-line Checkers and Their Use in Verification and Testing
Pages:8-15
Place:SK
Year:2009
Journal:Acta Electrotechnica et Informatica, Vol. 2009, No. 3, SK
ISSN:1335-8243
Keywords
on-line checker, on-line testing, verification, communication protocol, PSL, FoCs, ModelSim, FPGA
Annotation
In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. The results and compare of both methodologies are described. The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.
BibTeX:
@ARTICLE{
   author = {Zdeněk Kotásek and Martin Straka},
   title = {The Design of On-line Checkers and Their Use in Verification
	and Testing},
   pages = {8--15},
   journal = {Acta Electrotechnica et Informatica},
   volume = {2009},
   number = {3},
   year = {2009},
   ISSN = {1335-8243},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9009}
}