Conference paper

VAŠÍČEK, Z. and SEKANINA, L.. Efficient Hardware Accelerator for Symbolic Regression Problems. In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009, pp. 192-199. ISBN 978-80-87342-04-6.
Publication language:english
Original title:Efficient Hardware Accelerator for Symbolic Regression Problems
Title (cs):Efektivní hardwarový akcelerátor pro řešení problému symbolické regrese
Pages:192-199
Proceedings:5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Conference:MEMICS'09 -- 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Place:Znojmo, CZ
Year:2009
ISBN:978-80-87342-04-6
Publisher:Masaryk University
Files: 
+Type Name Title Size Modified
iconpaper.pdf546 KB2010-01-19 14:05:17
^ Select all
With selected:
Keywords
hardware acceleration, regression problem, evolutionary design, image filter, fpga, powerpc
Annotation
In this paper, a new hardware architecture for the acceleration of symbolic regression problems using Cartesian Genetic Programming (CGP) is presented.
In order to minimize the number of expensive memory accesses, a new algorithm is proposed.
The search algorithm is implemented using PowerPC processor which is available in Xilinx FPGAs of Virtex family.
A significant speedup of evolution is obtained in comparison with a highly optimized software implementation of CGP.
BibTeX:
@INPROCEEDINGS{
   author = {Zdeněk Vašíček and Lukáš Sekanina},
   title = {Efficient Hardware Accelerator for Symbolic Regression
	Problems},
   pages = {192--199},
   booktitle = {5th Doctoral Workshop on Mathematical and Engineering
	Methods in Computer Science},
   year = {2009},
   location = {Znojmo, CZ},
   publisher = {Masaryk University},
   ISBN = {978-80-87342-04-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.en?id=9108}
}

Your IPv4 address: 54.226.252.142
Switch to IPv6 connection

DNSSEC [dnssec]