Conference paper

 
Přikryl, Z., Hruška, T.: Cycle Accurate Profiler for ASIPs, In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2009, p. 168-175, ISBN 978-80-87342-04-6
Publication language:english
Original title:Cycle Accurate Profiler for ASIPs
Title (cs):Profiler pro ASIP na úrovni cyklů
Pages:168-175
Proceedings:5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Conference:MEMICS'09 -- 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Place:Brno, CZ
Year:2009
ISBN:978-80-87342-04-6
Publisher:Masaryk University
Keywords
Profiler, Simulation, Application Specific Instruction-set Processors, Formal Models
Annotation
The simulation of one processor on another is an important part of processor development because simulation is the way in witch a designer can verify and validate processor's instruction set, its micro-architecture or program, which will be executed on this processor. But a simple simulation is not sufficient in cases where the developer wants to optimize an executed program or processor's parts. For this purpose a profiler is used. The profiler is a tool tracing processor activities, so it provides the information about utilization of particular parts. In this paper a technique creating a profiler from a processor description in an architecture description language is proposed.
BibTeX:
@INPROCEEDINGS{
   author = {Zdeněk Přikryl and Tomáš Hruška},
   title = {Cycle Accurate Profiler for ASIPs},
   pages = {168--175},
   booktitle = {5th Doctoral Workshop on Mathematical and Engineering
	Methods in Computer Science},
   year = {2009},
   location = {Brno, CZ},
   publisher = {Masaryk University},
   ISBN = {978-80-87342-04-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9110}
}