Conference paper

STRAKA, M., KAŠTIL, J. and KOTÁSEK, Z.. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. In: Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010, pp. 173-176. ISBN 978-1-4244-6610-8.
Publication language:english
Original title:Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs
Title (cs):Pokročilé architektury odolné proti poruchám založené na částečné dynamické rekonfiguraci
Pages:173-176
Proceedings:Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
Conference:IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2010
Place:Wien, AT
Year:2010
ISBN:978-1-4244-6610-8
Publisher:IEEE Computer Society
Keywords
fault tolerant, on-line checker, architecture, triple modular redundancy, duplex, FPGA, partial reconfiguration
Annotation

Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

Abstract

Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

BibTeX:
@INPROCEEDINGS{
   author = {Martin Straka and Jan Kaštil and Zdeněk Kotásek},
   title = {Modern Fault Tolerant Architectures Based on Partial Dynamic
	Reconfiguration in FPGAs},
   pages = {173--176},
   booktitle = {Proceedings of the 2010 IEEE Symposium on Design and
	Diagnostics of Electronic Circuits and Systems DDECS 2010},
   year = {2010},
   location = {Wien, AT},
   publisher = {IEEE Computer Society},
   ISBN = {978-1-4244-6610-8},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.en?id=9177}
}

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