Conference paper

STRAKA, M., KAŠTIL, J. and KOTÁSEK, Z.. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. In: 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010, pp. 365-372. ISBN 978-0-7695-4171-6.
Publication language:english
Original title:Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration
Title (cs):Struktura odolného systému pro SRAM FPGA s využitím částečné dynamické rekonfigurace
Pages:365-372
Proceedings:13th EUROMICRO Conference on Digital System Design, DSD'2010
Conference:13th EUROMICRO Conference on Digital System Design, DSD'2010
Place:Lille, FR
Year:2010
ISBN:978-0-7695-4171-6
Publisher:IEEE Computer Society
Keywords
fault tolerant systems, reconfiguration, controller, FPGA, architecture
Annotation

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

Abstract

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

BibTeX:
@INPROCEEDINGS{
   author = {Martin Straka and Jan Kaštil and Zdeněk Kotásek},
   title = {Fault Tolerant Structure for SRAM-based FPGA via Partial
	Dynamic Reconfiguration},
   pages = {365--372},
   booktitle = {13th EUROMICRO Conference on Digital System Design, DSD'2010},
   year = {2010},
   location = {Lille, FR},
   publisher = {IEEE Computer Society},
   ISBN = {978-0-7695-4171-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.en?id=9208}
}

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