Conference paper

STRAKA, M., KAŠTIL, J. and KOTÁSEK, Z.. Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA. In: NORCHIP 2010. Tampere: IEEE Computer Society, 2010, pp. 1-4. ISBN 978-1-4244-8971-8.
Publication language:english
Original title:Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA
Title (cs):Generický řadič částečné dynamické rekonfigurace pro systémy odolné proti poruchám implementované v FPGA
Pages:1-4
Proceedings:NORCHIP 2010
Conference:NORCHIP conference 2010
Place:Tampere, FI
Year:2010
ISBN:978-1-4244-8971-8
Publisher:IEEE Computer Society
Keywords
FPGA, partial reconfiguration, controller, fault tolerant system, architecture
Annotation
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.
Abstract
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.
BibTeX:
@INPROCEEDINGS{
   author = {Martin Straka and Jan Kaštil and Zdeněk Kotásek},
   title = {Generic Partial Dynamic Reconfiguration Controller for Fault
	Tolerant Designs Based on FPGA},
   pages = {1--4},
   booktitle = {NORCHIP 2010},
   year = {2010},
   location = {Tampere, FI},
   publisher = {IEEE Computer Society},
   ISBN = {978-1-4244-8971-8},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.en?id=9353}
}

Your IPv4 address: 54.204.182.118
Switch to IPv6 connection

DNSSEC [dnssec]