| Vašíček, Z.: Využití a akcelerace evolučních technik pro návrh číslicových obvodů, In: Počítačové architektury a diagnostika 2010, Brno, CZ, FIT VUT, 2010, p. 165-170, ISBN 978-80-214-4140-8 | | Publication language: | czech |
|---|
| Original title: | Využití a akcelerace evolučních technik pro návrh číslicových obvodů |
|---|
| Title (en): | The evolutionary techniques for digital circuits : acceleration and applications |
|---|
| Pages: | 165-170 |
|---|
| Proceedings: | Počítačové architektury a diagnostika 2010 |
|---|
| Conference: | Počítačové architektury a diagnostika 2010, PAD 2010 |
|---|
| Place: | Brno, CZ |
|---|
| Year: | 2010 |
|---|
| ISBN: | 978-80-214-4140-8 |
|---|
| Publisher: | Faculty of Information Technology BUT |
|---|
| Keywords |
|---|
| evolutionary design, digital circuits, cartessian genetic programming, acceleration, fpga |
| Annotation |
|---|
| In recent years, it has been shown that by means of evolutionary techniques we can obtain quality and sometimes innovative solutions (especially in the field of digital system design). However, evolutionary approach are seldom applicable to solve complex tasks due to the so called scalability problem, in particular the problem of scalability of evaluation. This paper describes the structure of the dissertation thesis that proposes various approaches that can reduce the scalability problem in evolutionary design. |
| BibTeX: |
|---|
@INPROCEEDINGS{
author = {Zdeněk Vašíček},
title = {Využití a akcelerace evolučních technik pro návrh
číslicových obvodů},
pages = {165--170},
booktitle = {Počítačové architektury a diagnostika 2010},
year = {2010},
location = {Brno, CZ},
publisher = {Faculty of Information Technology BUT},
ISBN = {978-80-214-4140-8},
language = {czech},
url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9402}
} |
|
Faculty of Information Technology