Journal article

VAŠÍČEK, Z. and SEKANINA, L.. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. Computing and Informatics. Bratislava: Slovak Academic Press, 2010, vol. 29, no. 6, pp. 1359-1371. ISSN 1335-9150.
Publication language:english
Original title:Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units
Title (cs):Obvodový akcelerátor pro kartézské genetické programování s násobnými fitness jednotkami
Pages:1359-1371
Place:SK
Year:2010
Journal:Computing and Informatics, Vol. 29, No. 6, Bratislava, SK
ISSN:1335-9150
Files: 
+Type Name Title Size Modified
icon11080.pdf254 KB2011-02-18 16:45:15
^ Select all
With selected:
Keywords

Cartesian genetic programming, hardware accelerator, evolutionary circuit design, FPGA

Annotation
A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution.
BibTeX:
@ARTICLE{
   author = {Zdeněk Vašíček and Lukáš Sekanina},
   title = {Hardware Accelerator of Cartesian Genetic Programming with
	Multiple Fitness Units},
   pages = {1359--1371},
   journal = {Computing and Informatics},
   volume = {29},
   number = {6},
   year = {2010},
   ISSN = {1335-9150},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.en?id=9421}
}

Your IPv4 address: 54.90.243.204
Switch to IPv6 connection

DNSSEC [dnssec]