Conference paper

 
Bartoš, P., Kotásek, Z., Dohnal, J.: Decreasing Test Time by Scan Chain Reorganization, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, p. 371-374, ISBN 978-1-4244-9753-9
Publication language:english
Original title:Decreasing Test Time by Scan Chain Reorganization
Title (cs):Zkracování doby aplikace testu přeuspořádáním scan řetězce
Pages:371-374
Proceedings:IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
Conference:IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011
Place:Cottbus, DE
Year:2011
ISBN:978-1-4244-9753-9
Publisher:IEEE Computer Society
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Keywords
scan chain, test, time, reordering, reorganization, physical, layout
Annotation
In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the
methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.
BibTeX:
@INPROCEEDINGS{
   author = {Pavel Bartoš and Zdeněk Kotásek and Jan Dohnal},
   title = {Decreasing Test Time by Scan Chain Reorganization},
   pages = {371--374},
   booktitle = {IEEE Design and Diagnostics of Electronic Circuits and
	Systems DDECS'2011},
   year = {2011},
   location = {Cottbus, DE},
   publisher = {IEEE Computer Society},
   ISBN = {978-1-4244-9753-9},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9556}
}