Conference paper

 
Puš, V.: Packet Classification Algorithms, In: Počítačové architektury a diagnostika, Stará Lesná, SK, FEI STUBA, 2011, p. 157-162, ISBN 978-80-227-3552-0
Publication language:english
Original title:Packet Classification Algorithms
Title (cs):Algoritmy klasifikace paketů
Pages:157-162
Proceedings:Počítačové architektury a diagnostika
Conference:Počítačové architektury a diagnostika 2011, PAD 2011
Place:Stará Lesná, SK
Year:2011
ISBN:978-80-227-3552-0
Publisher:Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava
Keywords
Packet Classification, FPGA, Optimization
Annotation
As network speeds are increasing, the demand for hardware
acceleration of packet classification in FPGAs or ASICs is growing.
Nowadays algorithms implemented in
hardware can achieve multigigabit speeds,
but they suffer with great memory overhead.
This paper presents three packet classification algorithms
with strong potential
for acceleration in ASIC or FPGA,
while the memory requirements are kept reasonably low.
BibTeX:
@INPROCEEDINGS{
   author = {Viktor Puš},
   title = {Packet Classification Algorithms},
   pages = {157--162},
   booktitle = {Počítačové architektury a diagnostika},
   year = {2011},
   location = {Stará Lesná, SK},
   publisher = {Faculty of Electrical Engineering and Information
	Technology, Slovak University of Technology in Bratislava},
   ISBN = {978-80-227-3552-0},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9650}
}