Conference paper

 
Straka, M., Kaštil, J., Novotný, J., Kotásek, Z.: Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, p. 397-398, ISBN 978-1-4244-9753-9
Publication language:english
Original title:Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA
Title (cs):Odolná sběrnice pro multi-jadrove systémy implementované do FPGA
Pages:397-398
Proceedings:IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
Conference:IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011
Place:Cottbus, DE
Year:2011
ISBN:978-1-4244-9753-9
Publisher:IEEE Computer Society
Keywords
FPGA, fault tolerant, bus, multicore, reconfiguration, on-line checker, TMR
Annotation
In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used in the dependable system. All experiments were done on the Virtex5 and Virtex6 platform.
BibTeX:
@INPROCEEDINGS{
   author = {Martin Straka and Jan Kaštil and Jaroslav Novotný and Zdeněk
	Kotásek},
   title = {Advanced Fault Tolerant Bus for Multicore System Implemented
	in FPGA},
   pages = {397--398},
   booktitle = {IEEE Design and Diagnostics of Electronic Circuits and
	Systems DDECS'2011},
   year = {2011},
   location = {Cottbus, DE},
   publisher = {IEEE Computer Society},
   ISBN = {978-1-4244-9753-9},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9492}
}