Conference paper

 
Sekanina, L.: Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates, In: 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Gliwice, PL, IEEE CS, 2007, p. 243-246, ISBN 1424411610
Publication language:english
Original title:Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
Title (cs):Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
Pages:243-246
Proceedings:2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Conference:The 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Place:Gliwice, PL
Year:2007
ISBN:1424411610
Publisher:IEEE Computer Society
URL:http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf [PDF]
Keywords
digital circuit, polymorphic gate, adder, testing
Annotation
TBD
BibTeX:
@INPROCEEDINGS{
   author = {Lukáš Sekanina},
   title = {Design and Analysis of a New Self-Testing Adder Which
	Utilizes Polymorphic Gates},
   pages = {243--246},
   booktitle = {2007 IEEE Workshop on Design and Diagnostics of Electronic
	Circuits and Systems},
   year = {2007},
   location = {Gliwice, PL},
   publisher = {IEEE Computer Society},
   ISBN = {1424411610},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8310}
}