Conference paper

 
Kořenek, J., Kobierský, P.: Intrusion Detection System Intended for Multigigabit Networks, In: 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, PL, IEEE CS, 2007, p. 361-364, ISBN 978-1-4244-1161-0
Publication language:english
Original title:Intrusion Detection System Intended for Multigigabit Networks
Title (cs):Systém pro detekci narušení počítačové sítě určeny pro multigigabitové sítě
Pages:361-364
Proceedings:2007 IEEE Design and Diagnostics of Electronic Circuits and Systems
Conference:The 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Place:Krakow, PL
Year:2007
ISBN:978-1-4244-1161-0
Publisher:IEEE Computer Society
Keywords
Traffic Scanner, Snort, IDS, pattern matching
Annotation
Network intrusion detection systems (IDS) are becoming an important tool for securing critical information and infrastructure. Current software-based IDS often fails to keep up with high-speed network links so a hardware based IDS is requested. This paper deals with design and implementation of complete hardware accelerated IDS solution based on Field-Programmable Gate Array (FPGA). Core generator for automatic mapping of IDS rules to FPGA logic was designed to assure fast packet classification and high speed pattern matching. Proposed architecture has been evaluated on a COMBO6X card with FPGA Virtex-II Pro. Using COMBO6X card theoretical throughput 6.4~Gbps was achieved for all Snort rules. The designed system can be configured by rules described in Snort format using web interface.
BibTeX:
@INPROCEEDINGS{
   author = {Jan Kořenek and Petr Kobierský},
   title = {Intrusion Detection System Intended for Multigigabit
	Networks},
   pages = {361--364},
   booktitle = {2007 IEEE Design and Diagnostics of Electronic Circuits and
	Systems},
   year = {2007},
   location = {Krakow, PL},
   publisher = {IEEE Computer Society},
   ISBN = {978-1-4244-1161-0},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8394}
}