Thesis Details

Generátor ladicího nástroje na čipu

Bachelor's Thesis Student: Hrbáček Radek Academic Year: 2010/2011 Supervisor: Hruška Tomáš, prof. Ing., CSc.
English title
On-Chip Debugger Generator
Language
Czech
Abstract
This bachelor's thesis deals with the design and implementation of an on-chip debugger and its connection to the hardware generated using software tools developed as a part of the Lissom project. The first part introduces the JTAG and Nexus 5001 standards, which the implemented interface complies with. The practical part includes detailed description of the developed tool and its testing. The result is a functional on-chip debugger that has been tested with the Codea processor on the FITKit educational platform.
Keywords

debugging, JTAG, Nexus 5001, Lissom, VHDL, embedded system

Department
Department of Information Systems FIT BUT
Degree Programme
Information Technology
Files
Status
defended, grade A
Date
13 June 2011
Reviewer
Mecera Martin, Ing.
Committee
Dvořák Václav, prof. Ing., DrSc. (DCSY FIT BUT), předseda
Bartík Vladimír, Ing., Ph.D. (DIFS FIT BUT), člen
Janoušek Vladimír, doc. Ing., Ph.D. (DITS FIT BUT), člen
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT), člen
Smrčka Aleš, Ing., Ph.D. (DITS FIT BUT), člen
Citation
HRBÁČEK, Radek. Generátor ladicího nástroje na čipu. Brno, 2011. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2011-06-13. Supervised by Hruška Tomáš. Available from: https://www.fit.vut.cz/study/thesis/12656/
BibTeX 
@bachelorsthesis{FITBT12656,
    author = "Radek Hrb\'{a}\v{c}ek",
    type = "Bachelor's thesis",
    title = "Gener\'{a}tor ladic\'{i}ho n\'{a}stroje na \v{c}ipu",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2011,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/12656/"
}

Theses

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