Thesis Details

Vytvoření modelu procesoru RISC-V

Bachelor's Thesis Student: Nosterský Milan Academic Year: 2015/2016 Supervisor: Hruška Tomáš, prof. Ing., CSc.

English title

RISC-V Model Creation

Language

Czech

Abstract

This bachelor thesis deals with the implementations of RISC-V processor model in the language for architecture description CodAL.The theoretical part of thesis is focused on the description of CodAL language and classification of processors. The practical part of thesis deals with the implementation of processor RISC-V on instruction accurate level and the model testing. The thesis also deals with the implementation of MMU, timer and analysis of the proxy kernel.

Keywords

CodAL, Codasip, processor, RISC-V, ADL, model, MMU, timer, proxy kernel

Department

Department of Information Systems FIT BUT

Degree Programme

Information Technology

Files

Status

defended, grade C

Date

13 June 2016

Reviewer

Zachariášová Marcela, Ing., Ph.D.

Committee

Schwarz Josef, doc. Ing., CSc. (DCSY FIT BUT), předseda
Peringer Petr, Dr. Ing. (DITS FIT BUT), člen
Ryšavý Ondřej, doc. Ing., Ph.D. (DIFS FIT BUT), člen
Szőke Igor, Ing., Ph.D. (DCGM FIT BUT), člen
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY FIT BUT), člen

Citation

NOSTERSKÝ, Milan. Vytvoření modelu procesoru RISC-V. Brno, 2016. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2016-06-13. Supervised by Hruška Tomáš. Available from: https://www.fit.vut.cz/study/thesis/17675/

BibTeX

@bachelorsthesis{FITBT17675,
    author = "Milan Nostersk\'{y}",
    type = "Bachelor's thesis",
    title = "Vytvo\v{r}en\'{i} modelu procesoru RISC-V",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2016,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/17675/"
}

Theses