Thesis Details

Simulátor procesoru s operací násobení

Bachelor's Thesis Student: Závada Vladislav Academic Year: 2015/2016 Supervisor: Kunovský Jiří, doc. Ing., CSc.
English title
Multiple Operation Simulation
Language
Czech
Abstract

This work deals with the numeric integration. The reader is acquainted with the numerical solution of differential equations using Taylor series method. Then describes the different variants integrators. The practical part describes the design double-input integrator with multiplication and its implementation in an FPGA. For this integrator is also provided a simulator demonstrate its function.

Keywords

diferential equation, numeric integration, Taylor series, integrator, controller, multiplication, simulation, VHDL, FPGA

Department
Degree Programme
Information Technology
Files
Status
defended, grade C
Date
16 June 2016
Reviewer
Committee
Hanáček Petr, doc. Dr. Ing. (DITS FIT BUT), předseda
Burget Lukáš, doc. Ing., Ph.D. (DCGM FIT BUT), člen
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT), člen
Peringer Petr, Dr. Ing. (DITS FIT BUT), člen
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Citation
ZÁVADA, Vladislav. Simulátor procesoru s operací násobení. Brno, 2016. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2016-06-16. Supervised by Kunovský Jiří. Available from: https://www.fit.vut.cz/study/thesis/18534/
BibTeX
@bachelorsthesis{FITBT18534,
    author = "Vladislav Z\'{a}vada",
    type = "Bachelor's thesis",
    title = "Simul\'{a}tor  procesoru s operac\'{i} n\'{a}soben\'{i}",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2016,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/18534/"
}
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