Thesis Details

Automatizace verifikace řízené pokrytím pro procesory ASIP

Bachelor's Thesis Student: Badáň Filip Academic Year: 2015/2016 Supervisor: Zachariášová Marcela, Ing., Ph.D.
English title
ASIPs Intelligent Testbench Automation
Language
Czech
Abstract
This thesis focuses on the proposal and implementation of intelligent testbench automation for application-specific processors. The main goal of the thesis is to connect UVM verification environment with already designed genetic algorithm and to prepare this verification environment for integration into Codasip Studio development environment. The core of the final solution is modification of UVM components in verification environment and communication between the genetic algorithm and the generator of random test applications.
Keywords

functional verification, genetic algorithm, UVM, SystemVerilog, Codasip Studio, ASIP processors

Department
Degree Programme
Information Technology
Files
Status
defended, grade A
Date
14 June 2016
Reviewer
Committee
Švéda Miroslav, prof. Ing., CSc. (DIFS FIT BUT), předseda
Fučík Otto, doc. Dr. Ing. (DCSY FIT BUT), člen
Očenášek Pavel, Mgr. Ing., Ph.D. (DIFS FIT BUT), člen
Szőke Igor, Ing., Ph.D. (DCGM FIT BUT), člen
Šátek Václav, Ing., Ph.D. (DITS FIT BUT), člen
Citation
BADÁŇ, Filip. Automatizace verifikace řízené pokrytím pro procesory ASIP. Brno, 2016. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2016-06-14. Supervised by Zachariášová Marcela. Available from: https://www.fit.vut.cz/study/thesis/18663/
BibTeX
@bachelorsthesis{FITBT18663,
    author = "Filip Bad\'{a}\v{n}",
    type = "Bachelor's thesis",
    title = "Automatizace verifikace \v{r}\'{i}zen\'{e} pokryt\'{i}m pro procesory ASIP",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2016,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/18663/"
}
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