Thesis Details

Akcelerace NATu a paketového filtru v FPGA pro 10G sítě

Bachelor's Thesis Student: Orsák Michal Academic Year: 2015/2016 Supervisor: Viktorin Jan, Ing.
English title
Acceleration of NAT and Packet Filter in FPGA for 10G Networks
Language
Czech
Abstract

This thesis deals with the design of a universal hardware acceleration unit for packet filtering in FPGA for 10G networks. Maximum count of rules is greatly increased by the use of external QDR-II memory. Parameters of accelerator are suitable for NAT, packet filtering and lawful interceptions. The platform uses variable number of processing units. One of them controls accelerator by USB port. The rest is used for network processing.

Keywords

NAT, FPGA, network filters, HLS, 10G Ethernet, AMBA AXI

Department
Department of Computer Systems FIT BUT
Degree Programme
Information Technology
Files
Status
defended, grade C
Date
14 June 2016
Reviewer
Kořenek Jan, doc. Ing., Ph.D.
Committee
Švéda Miroslav, prof. Ing., CSc. (DIFS FIT BUT), předseda
Fučík Otto, doc. Dr. Ing. (DCSY FIT BUT), člen
Očenášek Pavel, Mgr. Ing., Ph.D. (DIFS FIT BUT), člen
Szőke Igor, Ing., Ph.D. (DCGM FIT BUT), člen
Šátek Václav, Ing., Ph.D. (DITS FIT BUT), člen
Citation
ORSÁK, Michal. Akcelerace NATu a paketového filtru v FPGA pro 10G sítě. Brno, 2016. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2016-06-14. Supervised by Viktorin Jan. Available from: https://www.fit.vut.cz/study/thesis/18665/
BibTeX 
@bachelorsthesis{FITBT18665,
    author = "Michal Ors\'{a}k",
    type = "Bachelor's thesis",
    title = "Akcelerace NATu a paketov\'{e}ho filtru v FPGA pro 10G s\'{i}t\v{e}",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2016,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/18665/"
}

Theses

Back to top