Thesis Details
Implementace samoopravných kódů pro 100 Gb/s Ethernet
The thesis deals with the design of entire RS-FEC layer for the 100 Gb/s Ethernet according to IEEE 802.3-2015 standard including Reed-Solomon encoder and decoder. Text clarifies mathematical basis of finite fields, linear block codes, cyclic codes and particularly Reed-Solomon codes used in design.Design of RS-FEC layer transmit side has been adjusted for implementation in COMBO network cards which use Xilinx Virtex-7 FPGA and realized in VHDL. Encoder has been optimized in several steps - as for FPGA resource usage and as for VHDL code synthesis duration. Reduction of resource usage has been achieved by using pipelining thanks to properties of cyclic codes. Synthesis duration then by creating logic of encoder on gate level on its own. Resulting implementation has been tested in simulation and it is optimized enough for usage in FPGA for Ethernet implementation.It is possible to adapt both design and implementation for 400Gb/s Ethernet which does not exist yet at the time of design.
Reed-Solomon codes, RS-FEC, Galoise fields, finite fields, FPGA, 100GBASE, LR4, SR4, CR4, KP4, error correction, error-control coding
Dytrych Jaroslav, Ing., Ph.D. (DCGM FIT BUT), člen
Hrubý Martin, Ing., Ph.D. (DITS FIT BUT), člen
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Švéda Miroslav, prof. Ing., CSc. (DIFS FIT BUT), člen
@bachelorsthesis{FITBT19862,
author = "Jan Veleck\'{y}",
type = "Bachelor's thesis",
title = "Implementace samoopravn\'{y}ch k\'{o}d\r{u} pro 100 Gb/s Ethernet",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2017,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/19862/"
}