Thesis Details

Radarový signálový procesor v FPGA

Master's Thesis Student: Přívara Jan Academic Year: 2016/2017 Supervisor: Maršík Lukáš, Ing.
English title
Radar Signal Processor in FPGA
Language
Czech
Abstract

This work describes design and implementation of radar processor in FPGA. The theoretical part is focused on Doppler radar, principles of radar signal processing methods and target platform Xilinx Zynq. The next part describes design of radar processor including its individual components and the solution is implemented. FPGA components are written in VHDL language. In the end, the implementation is evaluated and possible continuation of this work is stated.

Keywords

radar signal processing, radar processor, Doppler radar, Doppler effect, discrete Fourier transform, fast Fourier transform, fft, embedded systems, hardware acceleration, FPGA, Zynq

Department
Degree Programme
Information Technology, Field of Study Computer and Embedded Systems
Files
Status
defended, grade A
Date
21 June 2017
Reviewer
Committee
Fučík Otto, doc. Dr. Ing. (DCSY FIT BUT), předseda
Češka Milan, prof. RNDr., CSc. (DITS FIT BUT), člen
Fiedler Petr, doc. Ing., Ph.D. (UAMT FEEC BUT), člen
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT), člen
Ryšavý Ondřej, doc. Ing., Ph.D. (DIFS FIT BUT), člen
Zachariášová Marcela, Ing., Ph.D. (DCSY FIT BUT), člen
Citation
PŘÍVARA, Jan. Radarový signálový procesor v FPGA. Brno, 2017. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2017-06-21. Supervised by Maršík Lukáš. Available from: https://www.fit.vut.cz/study/thesis/19134/
BibTeX
@mastersthesis{FITMT19134,
    author = "Jan P\v{r}\'{i}vara",
    type = "Master's thesis",
    title = "Radarov\'{y} sign\'{a}lov\'{y} procesor v FPGA",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2017,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/19134/"
}
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