Thesis Details

HW/SW Codesign for the Xilinx Zynq Platform

Master's Thesis Student: Viktorin Jan Academic Year: 2012/2013 Supervisor: Korček Pavol, Ing., Ph.D.
English title
HW/SW Codesign for the Xilinx Zynq Platform
Language
Czech
Abstract

This work describes a novel approach of HW/SW codesign on the Xilinx Zynq and similar platforms. It deals with interconnections between the Processing System (ARM Cortex-A9 MPCore) and the Programmable Logic (FPGA) to find an abstract and universal way to develop applications that are partially offloaded into the programmable hardware and that run in the Linux operating system. For that purpose a framework for HW/SW codesign on the Zynq and similar platforms is designed. No such framework is currently available.

Keywords

Zynq, Linux, FPGA, AXI, SoC, HW/SW Codesign

Department
Degree Programme
Information Technology, Field of Study Computer and Embedded Systems
Files
Status
defended, grade A
Date
19 June 2013
Reviewer
Committee
Dvořák Václav, prof. Ing., DrSc. (DCSY FIT BUT), předseda
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), člen
Křivka Zbyněk, Ing., Ph.D. (DIFS FIT BUT), člen
Ryšavý Ondřej, doc. Ing., Ph.D. (DIFS FIT BUT), člen
Vlček Karel, prof. Ing., CSc. (FAI UTB), člen
Citation
VIKTORIN, Jan. HW/SW Codesign for the Xilinx Zynq Platform. Brno, 2013. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2013-06-19. Supervised by Korček Pavol. Available from: https://www.fit.vut.cz/study/thesis/14453/
BibTeX
@mastersthesis{FITMT14453,
    author = "Jan Viktorin",
    type = "Master's thesis",
    title = "HW/SW Codesign for the Xilinx Zynq Platform",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2013,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/14453/"
}
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