Thesis Details

Akcelerace kompresního algoritmu LZ4 v FPGA

Master's Thesis Student: Marton Dominik Academic Year: 2016/2017 Supervisor: Matoušek Jiří, Ing., Ph.D.
English title
Acceleration of LZ4 Compression Algorithm in FPGA
Language
Czech
Abstract

This project describes the implementation of an LZ4 compression algorithm in a C/C++-like language, that can be used to generate VHDL programs for FPGA integrated circuits embedded in accelerated network interface controllers (NICs). Based on the algorithm specification, software versions of LZ4 compressor and decompressor are implemented, which are then transformed into a synthesizable language, that is then used to generate fully functional VHDL code for both components. Execution time and compression ratio of all implementations are then compared. The project also serves as a demonstration of usability and influence of high-level synthesis and high-level approach to design and implementation of hardware applications known from common programming languages.

Keywords

fast lossless compression, LZ4, dictionary-based compression algorithms, FPGA, Catapult, high-level synthesis

Department
Degree Programme
Information Technology, Field of Study Computer Networks and Communication
Files
Status
defended, grade A
Date
22 June 2017
Reviewer
Committee
Ryšavý Ondřej, doc. Ing., Ph.D. (DIFS FIT BUT), předseda
Drábek Vladimír, doc. Ing., CSc. (DCSY FIT BUT), člen
Hladká Eva, doc. RNDr., Ph.D. (FI MUNI), člen
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Rogalewicz Adam, doc. Mgr., Ph.D. (DITS FIT BUT), člen
Švéda Miroslav, prof. Ing., CSc. (DIFS FIT BUT), člen
Citation
MARTON, Dominik. Akcelerace kompresního algoritmu LZ4 v FPGA. Brno, 2017. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2017-06-22. Supervised by Matoušek Jiří. Available from: https://www.fit.vut.cz/study/thesis/18400/
BibTeX
@mastersthesis{FITMT18400,
    author = "Dominik Marton",
    type = "Master's thesis",
    title = "Akcelerace kompresn\'{i}ho algoritmu LZ4 v FPGA",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2017,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/18400/"
}
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