Title:  Logic Systems 

Code:  LOS 

Ac.Year:  ukončen 2004/2005 (Not opened) 

Term:  Winter 

Curriculums:  

Language:  Czech, English 

Public info:  http://www.fit.vutbr.cz/study/courses/LOS/public/ 

Credits:  5 

Completion:  examination (written) 

Type of instruction:  Hour/sem  Lectures  Sem. Exercises  Lab. exercises  Comp. exercises  Other 

Hours:  39  18  0  0  8 

 Examination  Tests  Exercises  Laboratories  Other 

Points:  60  40  0  0  0 



Guarantee:  Eysselt Miloš, Ing., CSc., DCSY 

Lecturer:  Eysselt Miloš, Ing., CSc., DCSY 
Instructor:  Eysselt Miloš, Ing., CSc., DCSY 

Faculty:  Faculty of Information Technology BUT 

Department:  Department of Computer Systems FIT BUT 

Prerequisites:  

Followups:  

 Learning objectives: 

  To obtain an overview and a fundamental knowledge of a practical use of selected methods for description, behaviour analysis and design of combinational and sequential logic networks which are inside digital equipments.  Description: 

  Boolean algebra, logic variables, logic functions, logic circuits. Standardized logic expressions: sumofproducts, productofsums. Reduction methods: cube, QuineMcCluskey tabular technique, map. Petrick covering method. Networks with NOT, AND, OR, NAND, and NOR elements. TANT and TONT networks. Basic arithmetic blocks. MSI blocks: MX, DC/DMX, ROM, GA, PAL, PLA. Finite state machines: Mealy machine, Moore machine. Flipflops and latches: D, T, RS, R, S, JK. Simple synchronized sequential networks: registers, counters. Simple fixed and microprogrammed control units. Simple asynchronous sequential networks.  Learning outcomes and competences: 

  An abitity to do a behaviour analysis, and to design simple digital equipments.  Syllabus of lectures: 


 Introduction, Boolean algebra, logic variables, logic functions.
 Logic elements, logic gates, logic networks. Models of logic functions: expression, table, Venn diagram, ncube, map, block, logic and functional diagram, graph. Combinative and sequential behaviours. Huffman diagram.
Basic electrical parameters and characteristics of logic elements.
 Logic expressions: sumofproducts, productofsums, mixed forms.
 QuineMcCluskey tabular reduction technique, a covering technique by Petrick.
 Logic maps minimization technique. Networks with NOT, AND and OR elements. Static and dynamic hazards. Design of hazardless networks.
 TANT (ThreeStage ANDNOT Gate Network with True Inputs) and TONT (ThreeStage ORNOT Gate Network with True Inputs) networks.
 Adders: half, full, serial, parallel, serialparallel, decimal. Subtractor. Multiplier.
 MSI and LSI (VLSI) blocks: MX, DC/DMX, ROM, GA, PLA, PAL, PLD. Design of simple networks with MSI blocks.
 Finite state machines (Mealy machine, Moore machine): representation in table, expression, map, state diagram, logic diagram.
 Flipflops and latches: D, T, RS, R, S, JK. RS latches based on NANDs, and NORs. Edgetriggered flipflops. Masterslave flipflops.
 Synchronous sequential networks based on flipflops.
 Registers, counters, shift registers.
 Microprogramming: an analysis of a controlled algorithm.
 Simple fixed control units. Simple microprogrammed control units.
 Simple asynchronous sequential networks.
 Syllabus of numerical exercises: 


 Boolean algebra, logic functions and their representations, a behaviour analysis of contact switch networks.
 Logic expressions. QiuneMcCluskey tabular reduction method, Petrick cover function.
 Reduction methods: Karnaugh maps, logic and functional diagrams.
 Logic functions implementation using SSI i.cs.
 Behaviour analysis of logic networks: signal races, hazards.
 Selected logic modules: adders, subtractor.
 State machines and their representations. Design of synchronized sequential networks.
 Design of logic networks based on MSI and LSI i.cs. Programmable logic devices (PLD): gate arrays, PROM, PLA, PAL.
 Syllabus of laboratory exercises: 

 SSI integrated circuits ("74" family): Implementation of simple combinational and sequential networks.  Syllabus  others, projects and individual work of students: 


 Design of a combinational network.
 Design of a synchronized sequential network.
 Fundamental literature: 


 McCluskey, E.J.: LOGIC DESIGN PRICIPLES. PrenticeHall, USA, ISBN 0135397685, 1986.
 Cheung, J.Y.  Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0314478280, 1990.
 Bolton, M.: Digital Systems Design with Programmable Logic. AddisonWesley Publishing Company, Cornwall, GB, ISBN 0201145456, 1990.
 Katz, R.H.: Contemporary Logic Design. AddisonWesley/BenjaminCummings Publishing CO, Redwood City, CA, USA, ISBN 0805327037, 1993.
 Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0792384563, 1999.
 Wakerly, J.F.: Digital Design Principles and Practices. Prentice Hall, USA, ISBN 0130555207, 2000.
 Maurer, P.M.: Logic Design. University of South Florida, WWW Edition.
 Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW Edition.
 Study literature: 


 Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE I. University of Alberta, Edmonton, CA, 2003.
 Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE II. University of Alberta, Edmonton, CA, 2003.
 Eysselt, M.: Logic Systems: Basic Set of Problems 1 (SSI Circuits Networks). Textbook of the FEECSBrno_UT, DCSEFEECSBrno_UT, Edited 1997, 1998.
 Eysselt, M.: Logic Systems: Basic Set of Problems 2 (MSI Circuits Networks). Textbook of the FEECSBrno_UT, DCSEFEECSBrno_UT, 1997.
 Eysselt, M.: Logic Systems: Binary Logic Elements (Grafic Symbols for Diagrams). Textbook the of the FEECSBrno_UT, DCSEFEECSBrno_UT, Edited 1997, 1998.
 Eysselt, M.: Logic Systems: Laboratory. Textbook of the FEECSBrno_UT, DCSEFEECSBrno_UT, Edited 1997, 1998.
 Eysselt, M.: Logic Systems: Slides'97 (A Set of Basic Slides). Textbook of the FEECSBrno_UT, DCSEFEECSBrno_UT, 1997 (updates: 1998, 1999, 2000, 2001).
 Eysselt, M.: Programmable Logic Devices (Foundations & Examples). Textbook of the FEECSBrno_UT, DCSEFEECSBrno_UT, 1997. Here is a WWW version, 2nd Edition, from Dec. 2002.
 Controlled instruction: 

  International students: Test, midterm exam, active participation on laboratory practice (supported by the homework), and final exam are monitored education parts. Test, midterm exam and laboratory practice (supported by the homework) are without alternative. Points for homework may be obtained at the last laboratory class after successful modelling of all laboratory statements. Final exam has one additional alternative.  Progress assessment: 

  International students: Test "15 points", midterm exam "25 points", homework and its evaluation in laboratory "5 points", final exam "55 points".  Exam prerequisites: 

  Requirements for class accreditation are not defined.  
