Title:

Personal Computers

Code:ITP
Ac.Year:2017/2018
Term:Summer
Curriculums:
ProgrammeBranchYearDuty
IT-BC-3BIT-Elective
IT-BC-3BIT2ndElective
Language:Czech
Public info:http://www.fit.vutbr.cz/study/courses/ITP/public/
Credits:5
Completion:examination (written)
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:2601600
 ExaminationTestsExercisesLaboratoriesOther
Points:60240160
Guarantee:Kotásek Zdeněk, doc. Ing., CSc., DCSY
Lecturer:Kotásek Zdeněk, doc. Ing., CSc., DCSY
Instructor:Grochol David, Ing., DCSY
Šimek Václav, Ing., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Prerequisites: 
Design of Computer Systems (INP), DCSY
Schedule:
DayLessonWeekRoomStartEndLect.Gr.St.G.EndG.
TuelecturelecturesG20214:0015:502BIAxxxx
TuelecturelecturesG20214:0015:502BIBxxxx
TuelecturelecturesG20214:0015:503BITxxxx
 
Learning objectives:
  To provide students with the information on personal computer structure, parameters, its component structure and trends for the future.
Description:
  The course will provide students with up-to-date information on personal computer technique. Students will acquire the information on the principles of personal computer structure, I/O buses, elementary principles of external adapter construction and buses for the communication with peripheral devices.
Learning outcomes and competences:
  Students will become acquainted with the principles of PC construction and certain typical peripheral devices construction. In laboratory tutorials the attention will be paid especially to the principles of peripheral device control.
Syllabus of lectures:
 
  • The Developmnent Stages of Personal Computers, Parameters, Concepts.
  • The Development Stages of Intel Microprocessor Architectures.
  • The Implementation of CISC and RISC Architectures in Intel Microprocessors - 1. 
  • The Implementation of CISC and RISC Arhitectures in Intel Microprocessors - 2.
  • Memory Organization, Elements, Technologies, Memory Addressing, I/O Ports Addressing. CMOS Memory.
  • Memory Organization, Elements, Technologies, Memory Addressing, I/O Ports Addressing. CMOS Memory. 
  • Cache Memory, its Organization and Implementation.  
  • The Principles of Peripheral Operations Control, PIO Modes, Interrupt Request, Direct Memory Access.
  • The Developmnent Stages of Personal Computer Buses.
  • Centronics, Its Structure and Communication.
  • The Principles of Personal Computer Adapter Design and Construction.
  • The Buses for Peripheral Operations Control.
  • LANs, components.
Syllabus of laboratory exercises:
 
  • Communication on ISA bus and the use of BootROM.
  • PC Power Consumption. 
  • VGA interface, signals analysis.  
  • HDD and S.M.A.R.T. technology.
  • Communication on ISA bus and servicing the IRQ.
  • PCI System Bus and address decoder.
  • VGA interface, FITkit platform.
  • PS/2 analysis.  
Fundamental literature:
 
  • Hans-Peter Messmer: The Indispensable PC Hardware Book, Addison-Wesley, 1997, England, ISBN 0-201-40399-4, 1384 pages
  • Hans-Peter Messmer: The Indispensable Pentium Book, Addison-Wesley, 1995, USA, ISBN 0-201-87727-9, 496 pages
  • Scott Mueller: Upgrading and Repairing PCs, QUE, 2008, ISBN 0-7897-3697-7, 1556 pages
  • Carl Hamacher, Zvonko Vranesic, Safwat Zaky: Computer Organization, McGraw Hill, 2002, ISBN 0-07-232086-9, 805 pages
  • William Stallings: Computer Organization and architecture, designing for performance, Prentice Hall, 2006, ISBN 0-13-185644-8, 778 pages
Study literature:
 
  • The texts of lectures in electronic form.
Controlled instruction:
  Attending lab experiments, mid-term exam passing.
Progress assessment:
  Written mid-term exam.