Title:

Advanced Digital Systems

Code:PCS
Ac.Year:2005/2006 (Not opened)
Term:Winter
Curriculums:
ProgrammeFieldYearDuty
IT-MSC-2MGM.-Elective
IT-MSC-2MIN.-Elective
IT-MSC-2MIS.-Elective
IT-MSC-2MPS-Elective
Language of Instruction:Czech, English
Credits:5
Completion:examination (written)
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:390085
 ExaminationTestsExercisesLaboratoriesOther
Points:50200030
Guarantor:Fučík Otto, doc. Dr. Ing., DCSY
Lecturer:Fučík Otto, doc. Dr. Ing., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
 
Learning objectives:
  To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.
Description:
  Combinational and sequential logic design techniques, algorithms, and tools review. Structured design concept. Design strategies. Design decomposition. Design tools. Introduction to VHDL Basic features of VHDL. Simulation and synthesis. Basic VHDL modeling techniques. Algorithmic level design. Register Level Design. HDL-based design techniques. Constrained design. ASIC and PLD design process. Fast prototyping. Modeling for synthesis. Top-down design methodology in VHDL. Design case study. Design automation algorithms. HW/SW co-design.
Knowledge and skills required for the course:
  Digital system design, basic programming skills.
Learning outcomes and competences:
  The students are able to design complex constrained digital systems using contemporary design techniques, hardware description language VHLD, and professional CAD tools.
Syllabus of lectures:
 
  • Combinational and sequential logic design techniques, algorithms, and tools review.
  • Structured design concept. Design strategies. Design decomposition. Design tools.
  • Introduction to VHDL
  • Basic features of VHDL. Simulation and synthesis.
  • Basic VHDL modeling techniques.
  • Algorithmic level design.
  • Register Level Design.
  • HDL-based design techniques. Constrained design.
  • ASIC and PLD design process. Fast prototyping.
  • Modeling for synthesis.
  • Top-down design methodology in VHDL.
  • Design case study.
  • Design automation algorithms. HW/SW co-design.
Syllabus of computer exercises:
 
  • Design, schematic diagram drawing, and simulation of a 4-bit full ripple-carry adder.
  • Combinational logic circuits modeling and simulation using VHDL.
  • Sequential logic circuits modeling and simulation using VHDL.
  • A 16-bit, in VHDL described, sequential multiplier modeling, simulation, and implementation.
Syllabus - others, projects and individual work of students:
 
  • Individual five-hour VHDL project.
Fundamental literature:
 
  • Armstrong, J.R., Gray F.G.: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000
Study literature:
 
  • Lecture notes
  • Internet
Progress assessment:
  Written mid-term exam, submitted 4 PC ab reports and project in due dates.
Exam prerequisites:
  Duty credit consists of mid-term exam passing, submitting of 4 PC lab reports and competing the project in due dates.
 

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