Title:

Logic Systems

Code:LOS
Ac.Year:ukončen 2002/2003
Term:Winter
Study plans:
ProgramBranchYearDuty
EI-BC-3VTB1st Stage/2nd YearCompulsory
EI-MSC-5VTI1st Stage/2nd YearCompulsory
Language:Czech, English
Public info:http://www.fit.vutbr.cz/study/courses/LOS/public/
Credits:5
Completion:examination (written)
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:3918008
 ExaminationTestsExercisesLaboratoriesOther
Points:6040000
Guarantee:Eysselt Miloš, Ing., CSc., DCSY
Lecturer:Eysselt Miloš, Ing., CSc., DCSY
Instructor:Eysselt Miloš, Ing., CSc., DCSY
Sekanina Lukáš, prof. Ing., Ph.D., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Prerequisites: 
Algebra and Graphs (AGR), DMAT
Circuit Theory (TOI), UTEE
Linear Algebra and Geometry (LAG), DMAT
Follow-ups:
Computer Organization and Architecture (VPO), FIT
Diagnosis and Safe Systems (DIA), FIT
Digital and Impulse Circuits (CIO), FIT
Fault-Tolerant Systems (SOP), FIT
 
Learning objectives:
To obtain an overview and a fundamental knowledge of a practical use of selected methods for description, behaviour analysis and design of combinational and sequential logic networks which are inside digital equipments.
Description:
Boolean algebra, logic variables, logic functions, logic circuits. Standardized logic expressions: sum-of-products, product-of-sums. Reduction methods: cube, Quine-McCluskey tabular technique, map. Petrick covering method. Networks with NOT, AND, OR, NAND, and NOR elements. TANT and TONT networks. Basic arithmetic blocks. MSI blocks: MX, DC/DMX, ROM, GA, PAL, PLA. Finite state machines: Mealy machine, Moore machine. Flip-flops and latches: D, T, R-S, R, S, J-K. Simple synchronized sequential networks: registers, counters. Simple fixed and microprogrammed control units. Simple asynchronous sequential networks.
Learning outcomes and competences:
An abitity to do a behaviour analysis, and to design simple digital equipments.
Syllabus of lectures:
  1. Introduction, Boolean algebra, logic variables, logic functions.
  2. Logic elements, logic gates, logic networks. Models of logic functions: expression, table, Venn diagram, n-cube, map, block, logic and functional diagram, graph. Combinative and sequential behaviours. Huffman diagram.
    Basic electrical parameters and characteristics of logic elements.
  3. Logic expressions: sum-of-products, product-of-sums, mixed forms.
  4. Quine-McCluskey's tabular reduction technique, a covering technique by Petrick.
  5. Logic maps minimization technique. Networks with NOT, AND and OR elements. Static and dynamic hazards. Design of hazardless networks.
  6. TANT (Three-Stage AND-NOT Gate Network with True Inputs) and TONT (Three-Stage OR-NOT Gate Network with True Inputs) networks.
  7. Adders: half, full, serial, parallel, serial-parallel, decimal. Subtractor. Multiplier.
  8. MSI and LSI (VLSI) blocks: MX, DC/DMX, ROM, GA, PLA, PAL, PLD. Design of simple networks with MSI blocks.
  9. Finite state machines (Mealy machine, Moore machine): representation in table, expression, map, state diagram, logic diagram.
  10. Flip-flops and latches: D, T, R-S, R, S, J-K. R-S latches based on NANDs, and NORs. Edge-triggered flip-flops. Master-slave flip-flops.
  11. Synchronous sequential networks based on flip-flops.
  12. Registers, counters, shift registers.
  13. Microprogramming: an analysis of a controlled algorithm.
  14. Simple fixed control units. Simple microprogrammed control units.
  15. Simple asynchronous sequential networks.
Syllabus of numerical exercises:
  1. Boolean algebra, logic functions and their representations, a behaviour analysis of contact switch networks.
  2. Logic expressions. Qiune-McCluskey tabular reduction method, Petrick's cover function.
  3. Reduction methods: Karnaugh maps, logic and functional diagrams.
  4. Logic functions implementation using SSI i.cs.
  5. Behaviour analysis of logic networks: signal races, hazards.
  6. Selected logic modules: adders, subtractor.
  7. State machines and their representations. Design of synchronized sequential networks.
  8. Design of logic networks based on MSI and LSI i.cs. Programmable logic devices (PLD): gate arrays, PROM, PLA, PAL.
Syllabus of laboratory exercises:
SSI integrated circuits ("74" family): Implementation of simple combinational and sequential networks.
Syllabus - others, projects and individual work of students:
  1. Design of a combinational network.
  2. Design of a synchronized sequential network.
Fundamental literature:
  1. McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
  2. Cheung, J.Y. - Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
  3. Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
  4. Katz, R.H.: Contemporary Logic Design. Addison-Wesley/Benjamin-Cummings Publishing CO, Redwood City, CA, USA, ISBN 0-8053-2703-7, 1993.
  5. Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
  6. Wakerly, J.F.: Digital Design Principles and Practices. Prentice Hall, USA, ISBN 0-13-055520-7, 2000.
  7. Maurer, P.M.: Logic Design. University of South Florida, WWW Edition.
  8. Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW Edition.
Study literature:
  1. Eysselt, M.: Logic Systems: Basic Set of Problems 1 (SSI Circuits Networks). Textbook of the FEECS-Brno_UT, DCSE-FEECS-Brno_UT, Edited 1997, 1998.
  2. Eysselt, M.: Logic Systems: Basic Set of Problems 2 (MSI Circuits Networks). Textbook of the FEECS-Brno_UT, DCSE-FEECS-Brno_UT, 1997.
  3. Eysselt, M.: Logic Systems: Binary Logic Elements (Grafic Symbols for Diagrams). Textbook the of the FEECS-Brno_UT, DCSE-FEECS-Brno_UT, Edited 1997, 1998.
  4. Eysselt, M.: Logic Systems: Laboratory. Textbook of the FEECS-Brno_UT, DCSE-FEECS-Brno_UT, Edited 1997, 1998.
  5. Eysselt, M.: Logic Systems: Slides'97 (A Set of Basic Slides). Textbook of the FEECS-Brno_UT, DCSE-FEECS-Brno_UT, 1997 (updates: 1998, 1999, 2000, 2001).
  6. Eysselt, M.: Programmable Logic Devices (Foundations & Examples). Textbook of the FEECS-Brno_UT, DCSE-FEECS-Brno_UT, 1997. Here is a WWW version, 2nd Edition, from Dec. 2002.
Controlled instruction:
International students: Test, midexam, active partipation on laboratory practice, project, and final exam are monitored education parts. Test and midexam are without alternative. Points for project may be obtained at the last laboratory class after successful modelling of all laboratory statements. Final exam has one additional alternative.
Progress assessment:
International students: Test "15 points", midexam "25 points", project and its evaluation in laboratory "5 points", final exam "55 points".
Exam prerequisites:
Requirements for class accreditation are not defined.