Title:

Diagnosis and Safe Systems

Code:DBS
Ac.Year:ukončen 2009/2010
Term:Winter
Study plans:
ProgramBranchYearDuty
IT-MSC-2MBI-Elective
IT-MSC-2MBS-Elective
IT-MSC-2MGM-Elective
IT-MSC-2MGM.-Elective
IT-MSC-2MIN-Elective
IT-MSC-2MIN.-Elective
IT-MSC-2MIS-Elective
IT-MSC-2MIS.-Elective
IT-MSC-2MMI-Elective
IT-MSC-2MMM-Elective
IT-MSC-2MPS2ndElective
IT-MSC-2MPV-Elective
IT-MSC-2MSK-Elective
Language:Czech
Credits:5
Completion:examination (written)
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:3910088
 ExaminationTestsExercisesLaboratoriesOther
Points:502001515
Guarantee:Drábek Vladimír, doc. Ing., CSc., DCSY
Lecturer:Drábek Vladimír, doc. Ing., CSc., DCSY
Instructor:Drábek Vladimír, doc. Ing., CSc., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Follow-ups:
Fault Tolerant Systems (SPP), DCSY
Substitute for:
Diagnosis and Safe Systems (DIA), DCSY
 
Learning objectives:
To give the students the knowledge of methods for generation the tests for logic circuits, minimization and compression algorithms, and approaches to the design of testable circuits.
Description:
Fault models of TTL, CMOS, PLA and bridge faults. Test generation methods. Structural tests. Functional tests. Sequential circuit testing. RTL level test generation. Random and pseudorandom test generation. Locating sequences. Fault dictionaries. Diagnostic data compression. Design for testability, structured methods. Built-in diagnosis. Memory testing. Processor and wiring testing. Fail-safe circuits. Instrumentation for diagnosis. Verification approaches.
Learning outcomes and competences:
Basic approaches to test generation and design for testability.
Syllabus of lectures:
  1. Poruchové modely obvodů TTL, CMOS, PLA, zkratů.
  2. Test generation approaches.
  3. Funkctional tests.
  4. Sequential circuit testing.
  5. Test generation at RTL level.
  6. Random and pseudorandom test generation.
  7. Location sequences.
  8. Fault dictionaries.
  9. Diagnostic data compression.
  10. Design for testability.
  11. Built-in diagnosis.
  12. Memory testing.
  13. Processor and wiring testing.
  14. Fail-safe circuits.
  15. Fault-tolerance priciples.
  16. Diagnostic equipment.
Syllabus of numerical exercises:
  1. Fault models for TTL, CMOS, PLA and bridge faults.
  2. Test generation approaches.
  3. Functional tests.
  4. Sequential circuit testing.
  5. RTL-level test generation.
  6. Random and pseudorandom test generation.
Syllabus of computer exercises:
  1. Adder with built-in self test.
  2. Linear feedback shift register.
  3. Linear cellular automata.
  4. Boundary scan testing.
  5. Memory testing.
Syllabus - others, projects and individual work of students:
Individually assigned topics.
Fundamental literature:
  1. Abramovici, M. - Breuer, M.A. - Friedman, A.D.: Digital Systems Testing and Testable Design, Computer Science Press, 1990
Study literature:
  1. Lecture notes in electronic formats.
Controlled instruction:
Mid-term exam, labs and a project.
Progress assessment:
Mid-term exam, labs and a project.
Exam prerequisites:
Pass a mid-term exam, labs and a project.