Title:  Digital Systems Design 

Code:  INC 

Ac.Year:  2010/2011 

Term:  Summer 

Curriculums:  

Language of Instruction:  Czech 

Credits:  5 

Completion:  examination (written) 

Type of instruction:  Hour/sem  Lectures  Seminar Exercises  Laboratory Exercises  Computer Exercises  Other 

Hours:  39  10  0  0  3 

 Exams  Tests  Exercises  Laboratories  Other 

Points:  55  25  0  0  20 



Guarantor:  Fučík Otto, doc. Dr. Ing. (DCSY) 

Lecturer:  Fučík Otto, doc. Dr. Ing. (DCSY) Kořenek Jan, Ing., Ph.D. (DCSY) Martínek Tomáš, Ing., Ph.D. (DCSY) 
Instructor:  Kořenek Jan, Ing., Ph.D. (DCSY) Martínek Tomáš, Ing., Ph.D. (DCSY) 

Faculty:  Faculty of Information Technology BUT 

Department:  Department of Computer Systems FIT BUT 

Prerequisites:  

Followups:  

Substitute for:  

 Learning objectives: 

  To obtain an overview and fundamental knowledge of a practical use of selected methods for description of combinational and sequential logic networks which are inside digital equipments. To learn how to analyze and design combinational logic devices. To learn how to analyze and design sequential logic devices. To learn about design of digital circuits consisting of combinational and sequential logic devices.  Description: 

  Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic. Boolean algebra, logic functions and their representations: logic expressions, reduction methods, design of combinational logic networks. Analysis of logic networks behaviour: signal races, hazards. Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit. Sequential logic networks, latches and flipflops. State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider. Design of simple digital equipment: design CAD tools, description tools, design strategy. Integrated circuits families: TTL, CMOS. Programmable logic devices: FPGA, PROM, PLA, PAL. Simple asynchronous networks: design, analysis of behaviour, hazards.  Knowledge and skills required for the course: 

  The sets, relations and mappings. Basic terms and axioms of Boolean algebra. The elementary notions of the graph theory. Rudiments of electrical engineering phenomena and basic active and passive electronic elements.  Learning outcomes and competences: 

  To obtain an overview and fundamental knowledge of a practical use of selected methods for description of combinational and sequential logic networks which are inside digital equipments. To learn how to analyze and design combinational logic devices. To learn how to analyze and design sequential logic devices. Mastering of design of digital circuits consisting of combinational and sequential logic devices.  Syllabus of lectures: 


 Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic.
 Boolean algebra, logic functions and their representations, logic expressions.
 Reduction methods: QiuneMcCluskey tabular method, Petrick's cover function.
 Reduction methods: Karnaugh maps, logic and functional diagrams.
 Analysis of logic networks behaviour: signal races, hazards.
 Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit.
 Sequential logic networks, latches and flipflops.
 State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider.
 Design of simple digital equipment: CAD tools, description tools, design strategy.
 Integrated circuits families: TTL, CMOS.
 Programmable logic devices: FPGA, PROM, PLA, PAL.
 Simple asynchronous networks: design, analysis of behaviour, hazards.
 Syllabus of numerical exercises: 


 Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic.
 Boolean algebra, logic functions and their representations, a behaviour analysis of contactswitch networks.
 Logic expressions. QiuneMcCluskey tabular reduction method, Petrick's cover function.
 Reduction methods: Karnaugh maps, logic and functional diagrams.
 Logic functions implementation using SSI i.cs. Behaviour analysis of logic networks: signal races, hazards.
 Selected logic modules: adders, subtractor.
 State machines and their representations. Design of synchronized sequential networks.
 Design of logic networks based on MSI and LSI i.cs. Programmable logic devices: gate arrays, PROM, PLA, PAL.
 Syllabus of computer exercises: 


 Introduction to a CAD software. Modelling of demo examples.
 Modelling of personally designed logic networks.
 Syllabus  others, projects and individual work of students: 


 Design of a combinational network.
 Design of a synchronized sequential network.
 Fundamental literature: 


 McCluskey, E.J.: LOGIC DESIGN PRICIPLES. PrenticeHall, USA, ISBN 0135397685, 1986.
 Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0314478280, 1990.
 Bolton, M.: Digital Systems Design with Programmable Logic. AddisonWesley Publishing Company, Cornwall, GB, ISBN 0201145456, 1990.
 Katz, R.H.: Contemporary Logic Design. AddisonWesley/BenjaminCummings Publishing CO, Redwood City, CA, USA, ISBN 0805327037, 1993.
 Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0792384563, 1999.
 Study literature: 


 Maurer, P.M.: Logic Design. University of South Florida, WWW Edition.
 Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW Edition.
 Bolton, M.: Digital Systems Design with Programmable Logic. AddisonWesley Publishing Company, Cornwall, GB, ISBN 0201145456, 1990.
 McCluskey, E.J.: LOGIC DESIGN PRICIPLES. PrenticeHall, USA, ISBN 0135397685, 1986.
 Cheung, J.Y.  Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0314478280, 1990.
 Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0792384563, 1999.
 Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE I. University of Alberta, Edmonton, CA, 2003.
 Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE II. University of Alberta, Edmonton, CA, 2003.
 Eysselt, M.: Digital Systems Design: Basic Set of Problems 1 (SSI Circuits Networks). StudentText of the FIT, Brno UT, 2003 (WWW version).
 Eysselt, M.: Digital Systems Design: Basic Set of Problems 2 (MSI Circuits Networks). StudentText of the FIT, Brno UT, 2003 (WWW version).
 Eysselt, M.: Digital Systems Design: Binary Logic Elements (Grafic Symbols for Diagrams). StudentText of the FIT, Brno UT, 2003 (WWW version).
 Eysselt, M.: Digital Systems Design: Laboratory (TTL Family Circuits and Functional Diagrams). StudentText of the FIT, Brno UT, 2003 (WWW version).
 Eysselt, M.: Digital Systems Design: Slides 2003 (Set of Basic Slides). StudentText of the FIT, Brno UT, 2003.
 Eysselt, M.: Digital Systems Design: Programmable Logic Devices (Foundations & Examples). StudentText of the FIT Brno UT, FIT Brno UT, 2003 (WWW version).
 Controlled instruction: 

  The knowledge of students is examined by the midexam (25 points), the project (20 points) and by the final exam. The final exam enrollment is conditioned by obtaining of min. 4 points from the project. The minimal number of points, which can be obtained from the final exam, is 25 (of 55 points). Otherwise, no points will be assigned to a student. The midterm exam is without correction eventuality. The final exam has two additional correction eventualities. Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action can be initiated.  Progress assessment: 

  Standard students in Czech Programme: 1) Midterm exam: 25 points. 2) Homework and its evaluation in PC laboratory: 20 points. 3) Final exam: 55 points. Passing bounary for ECTS assessment: 50 points.
International students: 1) Test: 20 points. 2) Midterm exam: 20 points. 3) Final exam: 60 points. Passing bounary for ECTS assessment: 50 points.  Exam prerequisites: 

  Requirements for class accreditation are not defined.  
