Title:

Digital Systems Design

Code:INCe
Ac.Year:2011/2012
Term:Winter
Study plans:
ProgramBranchYearDuty
IT-BC-1HBCH-Elective
IT-MGR-1HMGH-Elective
Language:English
Credits:5
Completion:examination (written)
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:2600026
 ExaminationTestsExercisesLaboratoriesOther
Points:6040000
Guarantee:Eysselt Miloš, Ing., CSc., DCSY
Lecturer:Eysselt Miloš, Ing., CSc., DCSY
Instructor:Eysselt Miloš, Ing., CSc., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Prerequisites: 
Discrete Mathematics (IDA), DMAT
Follow-ups:
Design of Computer Systems (INP), DCSY
Microprocessors and Embedded Systems (IMP), DCSY
Personal Computers (ITP), DCSY
Substitute for:
Logic Systems (LOS), DCSY
 
Learning objectives:
To obtain an overview and fundamental knowledge of a practical use of selected methods for description of combinational and sequential logic networks which are inside digital equipments. To learn how to analyze and design combinational logic devices. To learn how to analyze and design sequential logic devices. To learn about design of digital circuits consisting of combinational and sequential logic devices.
Description:
Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic. Boolean algebra, logic functions and their representations: logic expressions, reduction methods, design of combinational logic networks. Analysis of logic networks behaviour: signal races, hazards. Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit. Sequential logic networks, latches and flip-flops. State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider. Design of simple digital equipment: design CAD tools, description tools, design strategy. Integrated circuits families: SSI, MSI, LSI. Programmable logic devices: gate arrays, PROM, PLA, PAL. Simple asynchronous networks: design, analysis of behaviour, hazards.
Knowledge and skills required for the course:
The sets, relations and mappings. Basic terms and axioms of Boolean algebra. The elementary notions of the graph theory. Rudiments of electrical engineering phenomena and basic active and passive electronic elements.
Learning outcomes and competences:
To obtain an overview and fundamental knowledge of a practical use of selected methods for description of combinational and sequential logic networks which are inside digital equipments. To learn how to analyze and design combinational logic devices. To learn how to analyze and design sequential logic devices. Mastering of design of digital circuits consisting of combinational and sequential logic devices.
Syllabus of lectures:
  1. Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic.
  2. Boolean algebra, logic functions and their representations, logic expressions.
  3. Reduction methods: Qiune-McCluskey tabular method, Petrick's cover function.
  4. Reduction methods: Karnaugh maps, logic and functional diagrams.
  5. Analysis of logic networks behaviour: signal races, hazards.
  6. Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit.
  7. Sequential logic networks, latches and flip-flops.
  8. State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider.
  9. Integrated circuits families: SSI, MSI, LSI. Programmable logic devices: gate arrays, PROM, PLA, PAL.
  10. Simple asynchronous networks: design, analysis of behaviour, hazards.
Syllabus of numerical exercises:
  1. Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic.
  2. Boolean algebra, logic functions and their representations, a behaviour analysis of contact-switch networks.
  3. Logic expressions. Qiune-McCluskey tabular reduction method, Petrick's cover function.
  4. Reduction methods: Karnaugh maps, logic and functional diagrams.
  5. Logic functions implementation using SSI i.cs. Behaviour analysis of logic networks: signal races, hazards.
  6. Selected logic modules: adders, subtractor.
  7. State machines and their representations. Design of synchronized sequential networks.
  8. Design of logic networks based on MSI and LSI i.cs. Programmable logic devices: gate arrays, PROM, PLA, PAL.
Fundamental literature:
  1. McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
  2. Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
  3. Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
  4. Katz, R.H.: Contemporary Logic Design. Addison-Wesley/Benjamin-Cummings Publishing CO, Redwood City, CA, USA, ISBN 0-8053-2703-7, 1993.
  5. Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
Study literature:
  1. Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW Edition.
  2. Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
  3. McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
  4. Cheung, J.Y. - Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
  5. Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
  6. Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE I. University of Alberta, Edmonton, CA, 2003.
  7. Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE II. University of Alberta, Edmonton, CA, 2003.
  8. Eysselt, M.: Digital Systems Design: Basic Set of Problems 1 (SSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  9. Eysselt, M.: Digital Systems Design: Basic Set of Problems 2 (MSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  10. Eysselt, M.: Digital Systems Design: Binary Logic Elements (Grafic Symbols for Diagrams). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  11. Eysselt, M.: Digital Systems Design: Laboratory (TTL Family Circuits and Functional Diagrams). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  12. Eysselt, M.: Digital Systems Design: Slides 2003 (Set of Basic Slides). Student-Text of the FIT, Brno UT, 2003. 
  13. Eysselt, M.: Digital Systems Design: Programmable Logic Devices (Foundations & Examples). Student-Text of the FIT Brno UT, FIT Brno UT, 2003 (WWW version).
Controlled instruction:
Test, mid-term exam and final exam are the monitored, and points earning, education. Test and mid-term exam are without correction eventuality. Final exam has two additional correction eventualities.
Progress assessment:
1) Test: 20 points.
2) Mid-Semester exam: 20 points.
3) Final exam: 60 points.
Passing bounary for ECTS assessment: 50 points.
Exam prerequisites:
Requirements for class accreditation are not defined.