Title:

Digital Systems Design

Code:INC
Ac.Year:2012/2013
Term:Summer
Study plans:
ProgramBranchYearDuty
IT-BC-3BIT1stCompulsory
Language:Czech
Credits:5
Completion:accreditation+exam (written)
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:3910003
 ExaminationTestsExercisesLaboratoriesOther
Points:55250020
Guarantee:Fučík Otto, doc. Dr. Ing., DCSY
Lecturer:Fučík Otto, doc. Dr. Ing., DCSY
Kořenek Jan, Ing., Ph.D., DCSY
Martínek Tomáš, Ing., Ph.D., DCSY
Instructor:Kořenek Jan, Ing., Ph.D., DCSY
Martínek Tomáš, Ing., Ph.D., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Prerequisites: 
Discrete Mathematics (IDA), DMAT
Follow-ups:
Design of Computer Systems (INP), DCSY
Microprocessors and Embedded Systems (IMP), DCSY
Personal Computers (ITP), DCSY
Substitute for:
Logic Systems (LOS), DCSY
 
Learning objectives:
The goal is to obtain fundamental knowledge of methods for description, analysis, and design of combinational and sequential logic networks in digital systems.
Description:
Binary number system: positional notation, conversion of base, binary codes, binary arithmetic. Boolean algebra, logic functions and their representations: logic expressions, reduction methods, design of combinational logic networks. Analysis of logic networks behaviour: signal races, hazards. Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit. Simple asynchronous networks: design and analysis of behaviour. Sequential logic networks, latches and flip-flops. State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider. Design of simple digital equipment: design CAD tools, description tools, design strategy. Integrated circuits families. Programmable logic devices. 
Knowledge and skills required for the course:
The sets, relations and mappings. Basic terms and axioms of Boolean algebra. The elementary notions of the graph theory. Rudiments of electrical engineering phenomena and basic active and passive electronic elements.
Learning outcomes and competences:
Fundamental knowledge of selected methods for description, analysis and design of combinational and sequential logic in digital systems. 
Syllabus of lectures:
  1. Binary number system: positional notation, conversion of base, binary codes, binary arithmetic.
  2. Boolean algebra, logic functions and their representations, logic expressions.
  3. Reduction methods: Qiune-McCluskey tabular method, Petrick's cover function.
  4. Reduction methods: Karnaugh maps, logic and functional diagrams.
  5. Analysis of logic networks behaviour, signal races, hazards.
  6. Adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator.
  7. Arithmetic and logic unit.
  8. Simple asynchronous networks, latches and flip-flops.
  9. Sequential logic networks.
  10. State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider.
  11. Design of simple digital equipment: CAD tools, description tools, design strategy.
  12. Integrated circuits families. Programmable logic devices.
Syllabus of numerical exercises:
  1. Binary number system: positional notation, conversion of base, binary codes, binary arithmetic.
  2. Boolean algebra, logic functions and their representations, a behaviour analysis of contact-switch networks.
  3. Logic expressions. Qiune-McCluskey tabular reduction method, Petrick's cover function.
  4. Reduction methods: Karnaugh maps, logic and functional diagrams.
  5. Logic functions implementation using logic components.
  6. Selected logic modules: multiplexer, demultiplexer, encoder, decoder, adder, ALU.
  7. State machines and their representations. Design of synchronized sequential networks.
  8. Design of logic networks using programmable logic devices.
Syllabus of computer exercises:
  1. Introduction to a CAD software. Modelling of demo examples.
  2. Modelling of personally designed logic networks.
Syllabus - others, projects and individual work of students:
  1. Three-hour project.
Fundamental literature:
  1. McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
  2. Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
  3. Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
  4. Katz, R.H.: Contemporary Logic Design. Addison-Wesley/Benjamin-Cummings Publishing CO, Redwood City, CA, USA, ISBN 0-8053-2703-7, 1993.
  5. Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
Study literature:
  1. Maurer, P.M.: Logic Design. University of South Florida, WWW Edition.
  2. Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW Edition.
  3. Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
  4. McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
  5. Cheung, J.Y. - Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
  6. Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
  7. Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE I. University of Alberta, Edmonton, CA, 2003.
  8. Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE II. University of Alberta, Edmonton, CA, 2003.
  9. Eysselt, M.: Digital Systems Design: Basic Set of Problems 1 (SSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  10. Eysselt, M.: Digital Systems Design: Basic Set of Problems 2 (MSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  11. Eysselt, M.: Digital Systems Design: Binary Logic Elements (Grafic Symbols for Diagrams). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  12. Eysselt, M.: Digital Systems Design: Laboratory (TTL Family Circuits and Functional Diagrams). Student-Text of the FIT, Brno UT, 2003 (WWW version). 
  13. Eysselt, M.: Digital Systems Design: Slides 2003 (Set of Basic Slides). Student-Text of the FIT, Brno UT, 2003. 
  14. Eysselt, M.: Digital Systems Design: Programmable Logic Devices (Foundations & Examples). Student-Text of the FIT Brno UT, FIT Brno UT, 2003 (WWW version).
Controlled instruction:
The knowledge of students is examined by the mid-exam (20 points), the project (25 pints) and by the final exam. The minimal number of points, which can be obtained from the final exam, is 25 (of 55 points). Otherwise, no points will be assigned to a student. Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action can be initiated.
Progress assessment:
Standard students in Czech Programme:
1) Mid-term exam: 25 points.
2) Homework and its evaluation in PC laboratory: 20 points.
3) Final exam: 55 points.
Passing bounary for ECTS assessment: 50 points.

International students:
1) Test: 20 points.
2) Mid-term exam: 20 points.
3) Final exam: 60 points.
Passing bounary for ECTS assessment: 50 points.
Exam prerequisites:
For receiving the credit and thus for entering the exam, students have to obtain at least five points from the project. Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action may be initiated.